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https://github.com/torvalds/linux.git
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Merge branch 'bna-next'
Ivan Vecera says: ==================== bna: clean-up The patches clean the bna driver. v2: changes & comments requested by Joe ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
d0504f4d8f
@ -282,7 +282,6 @@ bfa_nw_cee_attach(struct bfa_cee *cee, struct bfa_ioc *ioc,
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cee->ioc = ioc;
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bfa_nw_ioc_mbox_regisr(cee->ioc, BFI_MC_CEE, bfa_cee_isr, cee);
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bfa_q_qe_init(&cee->ioc_notify);
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bfa_ioc_notify_init(&cee->ioc_notify, bfa_cee_notify, cee);
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bfa_nw_ioc_notify_register(cee->ioc, &cee->ioc_notify);
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}
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@ -28,19 +28,6 @@
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typedef void (*bfa_sm_t)(void *sm, int event);
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/* oc - object class eg. bfa_ioc
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* st - state, eg. reset
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* otype - object type, eg. struct bfa_ioc
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* etype - object type, eg. enum ioc_event
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*/
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#define bfa_sm_state_decl(oc, st, otype, etype) \
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static void oc ## _sm_ ## st(otype * fsm, etype event)
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#define bfa_sm_set_state(_sm, _state) ((_sm)->sm = (bfa_sm_t)(_state))
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#define bfa_sm_send_event(_sm, _event) ((_sm)->sm((_sm), (_event)))
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#define bfa_sm_get_state(_sm) ((_sm)->sm)
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#define bfa_sm_cmp_state(_sm, _state) ((_sm)->sm == (bfa_sm_t)(_state))
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/* For converting from state machine function to state encoding. */
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struct bfa_sm_table {
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bfa_sm_t sm; /*!< state machine function */
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@ -67,7 +54,6 @@ typedef void (*bfa_fsm_t)(void *fsm, int event);
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} while (0)
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#define bfa_fsm_send_event(_fsm, _event) ((_fsm)->fsm((_fsm), (_event)))
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#define bfa_fsm_get_state(_fsm) ((_fsm)->fsm)
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#define bfa_fsm_cmp_state(_fsm, _state) \
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((_fsm)->fsm == (bfa_fsm_t)(_state))
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@ -24,7 +24,6 @@
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#include "bfa_defs_status.h"
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#include "bfa_defs_mfg_comm.h"
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#define BFA_STRING_32 32
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#define BFA_VERSION_LEN 64
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/* ---------------------- adapter definitions ------------ */
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@ -55,7 +54,7 @@ struct bfa_adapter_attr {
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char optrom_ver[BFA_VERSION_LEN];
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char os_type[BFA_ADAPTER_OS_TYPE_LEN];
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struct bfa_mfg_vpd vpd;
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struct mac mac;
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u8 mac[ETH_ALEN];
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u8 nports;
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u8 max_speed;
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@ -187,8 +186,6 @@ enum {
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#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
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#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
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#pragma pack(1)
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/* BFA adapter manufacturing block definition.
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*
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* All numerical fields are in big-endian format.
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@ -211,7 +208,7 @@ struct bfa_mfg_block {
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char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
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char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
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char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
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mac_t mfg_mac; /* base mac address */
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u8 mfg_mac[ETH_ALEN]; /* base mac address */
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u8 num_mac; /* number of mac addresses */
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u8 rsv2;
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u32 card_type; /* card type */
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@ -227,9 +224,7 @@ struct bfa_mfg_block {
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char initial_mode[8]; /* initial mode: hba/cna/nic */
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u8 rsv4[84];
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u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /* md5 checksum */
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};
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#pragma pack()
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} __packed;
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/* ---------------------- pci definitions ------------ */
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@ -109,8 +109,6 @@ union bfa_port_stats_u {
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struct bfa_port_eth_stats eth;
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};
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#pragma pack(1)
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#define BFA_CEE_LLDP_MAX_STRING_LEN (128)
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#define BFA_CEE_DCBX_MAX_PRIORITY (8)
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#define BFA_CEE_DCBX_MAX_PGID (8)
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@ -133,7 +131,7 @@ struct bfa_cee_lldp_str {
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u8 len;
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u8 rsvd[2];
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u8 value[BFA_CEE_LLDP_MAX_STRING_LEN];
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};
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} __packed;
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/* LLDP parameters */
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struct bfa_cee_lldp_cfg {
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@ -145,7 +143,7 @@ struct bfa_cee_lldp_cfg {
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struct bfa_cee_lldp_str mgmt_addr;
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u16 time_to_live;
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u16 enabled_system_cap;
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};
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} __packed;
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enum bfa_cee_dcbx_version {
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DCBX_PROTOCOL_PRECEE = 1,
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@ -171,7 +169,7 @@ struct bfa_cee_dcbx_cfg {
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u8 lls_fcoe; /* FCoE Logical Link Status */
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u8 lls_lan; /* LAN Logical Link Status */
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u8 rsvd[2];
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};
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} __packed;
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/* CEE status */
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/* Making this to tri-state for the benefit of port list command */
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@ -188,11 +186,11 @@ struct bfa_cee_attr {
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u8 error_reason;
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struct bfa_cee_lldp_cfg lldp_remote;
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struct bfa_cee_dcbx_cfg dcbx_remote;
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mac_t src_mac;
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u8 src_mac[ETH_ALEN];
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u8 link_speed;
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u8 nw_priority;
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u8 filler[2];
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};
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} __packed;
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/* LLDP/DCBX/CEE Statistics */
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struct bfa_cee_stats {
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@ -214,8 +212,6 @@ struct bfa_cee_stats {
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u32 cee_status_up; /*!< CEE status up */
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u32 cee_hw_cfg_changed; /*!< CEE hw cfg changed */
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u32 cee_rx_invalid_cfg; /*!< CEE invalid cfg */
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};
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#pragma pack()
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} __packed;
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#endif /* __BFA_DEFS_CNA_H__ */
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@ -59,8 +59,6 @@ enum {
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BFA_MFG_TYPE_INVALID = 0, /*!< Invalid card type */
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};
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#pragma pack(1)
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/* Check if Mezz card */
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#define bfa_mfg_is_mezz(type) (( \
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(type) == BFA_MFG_TYPE_JAYHAWK || \
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@ -77,7 +75,7 @@ enum {
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CB_GPIO_FC4P2 = (4), /*!< 4G 2port FC card */
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CB_GPIO_FC4P1 = (5), /*!< 4G 1port FC card */
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CB_GPIO_DFLY = (6), /*!< 8G 2port FC mezzanine card */
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CB_GPIO_PROTO = (1 << 7) /*!< 8G 2port FC prototypes */
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CB_GPIO_PROTO = BIT(7) /*!< 8G 2port FC prototypes */
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};
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#define bfa_mfg_adapter_prop_init_gpio(gpio, card_type, prop) \
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@ -148,8 +146,6 @@ struct bfa_mfg_vpd {
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u8 len; /*!< vpd data length excluding header */
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u8 rsv;
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u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */
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};
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#pragma pack()
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} __packed;
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#endif /* __BFA_DEFS_MFG_H__ */
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@ -23,14 +23,6 @@
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/* IOC local definitions */
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#define bfa_ioc_state_disabled(__sm) \
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(((__sm) == BFI_IOC_UNINIT) || \
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((__sm) == BFI_IOC_INITING) || \
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((__sm) == BFI_IOC_HWINIT) || \
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((__sm) == BFI_IOC_DISABLED) || \
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((__sm) == BFI_IOC_FAIL) || \
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((__sm) == BFI_IOC_CFG_DISABLED))
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/* Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. */
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#define bfa_ioc_firmware_lock(__ioc) \
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@ -57,12 +49,6 @@
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((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc))
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#define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \
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((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate))
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#define bfa_ioc_get_alt_ioc_fwstate(__ioc) \
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((__ioc)->ioc_hwif->ioc_get_alt_fwstate(__ioc))
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#define bfa_ioc_mbox_cmd_pending(__ioc) \
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(!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
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readl((__ioc)->ioc_regs.hfn_mbox_cmd))
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static bool bfa_nw_auto_recover = true;
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@ -1105,12 +1091,9 @@ static void
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bfa_ioc_event_notify(struct bfa_ioc *ioc, enum bfa_ioc_event event)
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{
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struct bfa_ioc_notify *notify;
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struct list_head *qe;
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list_for_each(qe, &ioc->notify_q) {
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notify = (struct bfa_ioc_notify *)qe;
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list_for_each_entry(notify, &ioc->notify_q, qe)
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notify->cbfn(notify->cbarg, event);
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}
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}
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static void
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@ -1387,7 +1370,7 @@ static enum bfi_ioc_img_ver_cmp
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bfa_ioc_fw_ver_patch_cmp(struct bfi_ioc_image_hdr *base_fwhdr,
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struct bfi_ioc_image_hdr *fwhdr_to_cmp)
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{
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if (bfa_ioc_fw_ver_compatible(base_fwhdr, fwhdr_to_cmp) == false)
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if (!bfa_ioc_fw_ver_compatible(base_fwhdr, fwhdr_to_cmp))
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return BFI_IOC_IMG_VER_INCOMP;
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if (fwhdr_to_cmp->fwver.patch > base_fwhdr->fwver.patch)
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@ -1398,7 +1381,7 @@ bfa_ioc_fw_ver_patch_cmp(struct bfi_ioc_image_hdr *base_fwhdr,
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/* GA takes priority over internal builds of the same patch stream.
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* At this point major minor maint and patch numbers are same.
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*/
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if (fwhdr_is_ga(base_fwhdr) == true)
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if (fwhdr_is_ga(base_fwhdr))
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if (fwhdr_is_ga(fwhdr_to_cmp))
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return BFI_IOC_IMG_VER_SAME;
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else
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@ -1912,10 +1895,8 @@ bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
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}
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void
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bfa_nw_ioc_timeout(void *ioc_arg)
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bfa_nw_ioc_timeout(struct bfa_ioc *ioc)
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{
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struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
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bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
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}
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@ -1980,10 +1961,9 @@ bfa_ioc_send_getattr(struct bfa_ioc *ioc)
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}
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void
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bfa_nw_ioc_hb_check(void *cbarg)
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bfa_nw_ioc_hb_check(struct bfa_ioc *ioc)
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{
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struct bfa_ioc *ioc = cbarg;
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u32 hb_count;
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u32 hb_count;
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hb_count = readl(ioc->ioc_regs.heartbeat);
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if (ioc->hb_count == hb_count) {
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@ -2177,7 +2157,8 @@ bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
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/**
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* Enqueue command to firmware.
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*/
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bfa_q_deq(&mod->cmd_q, &cmd);
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cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
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list_del(&cmd->qe);
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bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
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/**
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@ -2198,8 +2179,10 @@ bfa_ioc_mbox_flush(struct bfa_ioc *ioc)
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struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
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struct bfa_mbox_cmd *cmd;
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while (!list_empty(&mod->cmd_q))
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bfa_q_deq(&mod->cmd_q, &cmd);
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while (!list_empty(&mod->cmd_q)) {
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cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe);
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list_del(&cmd->qe);
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}
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}
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/**
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@ -2223,7 +2206,7 @@ bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz)
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/*
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* Hold semaphore to serialize pll init and fwtrc.
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*/
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if (bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg) == 0)
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if (!bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg))
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return 1;
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writel(pgnum, ioc->ioc_regs.host_page_num_fn);
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@ -2278,7 +2261,7 @@ bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc)
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int tlen;
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if (ioc->dbg_fwsave_once) {
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ioc->dbg_fwsave_once = 0;
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ioc->dbg_fwsave_once = false;
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if (ioc->dbg_fwsave_len) {
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tlen = ioc->dbg_fwsave_len;
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bfa_nw_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen);
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@ -2796,7 +2779,7 @@ bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
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ad_attr->prototype = 0;
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ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
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ad_attr->mac = bfa_nw_ioc_get_mac(ioc);
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bfa_nw_ioc_get_mac(ioc, ad_attr->mac);
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ad_attr->pcie_gen = ioc_attr->pcie_gen;
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ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
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@ -2942,10 +2925,10 @@ bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
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return ioc->attr->pwwn;
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}
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mac_t
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bfa_nw_ioc_get_mac(struct bfa_ioc *ioc)
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void
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bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac)
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{
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return ioc->attr->mac;
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ether_addr_copy(mac, ioc->attr->mac);
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}
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/* Firmware failure detected. Start recovery actions. */
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@ -2997,9 +2980,8 @@ bfa_iocpf_stop(struct bfa_ioc *ioc)
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}
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void
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bfa_nw_iocpf_timeout(void *ioc_arg)
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bfa_nw_iocpf_timeout(struct bfa_ioc *ioc)
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{
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struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
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enum bfa_iocpf_state iocpf_st;
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iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
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@ -3011,10 +2993,8 @@ bfa_nw_iocpf_timeout(void *ioc_arg)
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}
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void
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bfa_nw_iocpf_sem_timeout(void *ioc_arg)
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bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc)
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{
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struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
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bfa_ioc_hw_sem_get(ioc);
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}
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@ -3245,7 +3225,6 @@ bfa_nw_flash_attach(struct bfa_flash *flash, struct bfa_ioc *ioc, void *dev)
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flash->op_busy = 0;
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bfa_nw_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash);
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bfa_q_qe_init(&flash->ioc_notify);
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bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash);
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list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q);
|
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}
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|
@ -232,12 +232,6 @@ struct bfa_ioc_hwif {
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#define bfa_ioc_asic_gen(__ioc) ((__ioc)->asic_gen)
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#define bfa_ioc_is_default(__ioc) \
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(bfa_ioc_pcifn(__ioc) == bfa_ioc_portid(__ioc))
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#define bfa_ioc_fetch_stats(__ioc, __stats) \
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(((__stats)->drv_stats) = (__ioc)->stats)
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#define bfa_ioc_clr_stats(__ioc) \
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memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
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#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
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#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
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#define bfa_ioc_speed_sup(__ioc) \
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BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
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#define bfa_ioc_get_nports(__ioc) \
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@ -268,13 +262,6 @@ void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
|
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((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
|
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(__ioc)->asic_mode))
|
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|
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#define bfa_ioc_isr_mode_set(__ioc, __msix) do { \
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if ((__ioc)->ioc_hwif->ioc_isr_mode_set) \
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((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)); \
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} while (0)
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#define bfa_ioc_ownership_reset(__ioc) \
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((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
|
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#define bfa_ioc_lpu_read_stat(__ioc) do { \
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if ((__ioc)->ioc_hwif->ioc_lpu_read_stat) \
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((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc)); \
|
||||
@ -309,7 +296,7 @@ void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
|
||||
struct bfi_ioc_image_hdr *fwhdr);
|
||||
bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
|
||||
struct bfi_ioc_image_hdr *fwhdr);
|
||||
mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
|
||||
void bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac);
|
||||
void bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave);
|
||||
int bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen);
|
||||
int bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen);
|
||||
@ -317,10 +304,10 @@ int bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen);
|
||||
/*
|
||||
* Timeout APIs
|
||||
*/
|
||||
void bfa_nw_ioc_timeout(void *ioc);
|
||||
void bfa_nw_ioc_hb_check(void *ioc);
|
||||
void bfa_nw_iocpf_timeout(void *ioc);
|
||||
void bfa_nw_iocpf_sem_timeout(void *ioc);
|
||||
void bfa_nw_ioc_timeout(struct bfa_ioc *ioc);
|
||||
void bfa_nw_ioc_hb_check(struct bfa_ioc *ioc);
|
||||
void bfa_nw_iocpf_timeout(struct bfa_ioc *ioc);
|
||||
void bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc);
|
||||
|
||||
/*
|
||||
* F/W Image Size & Chunk
|
||||
|
@ -24,7 +24,7 @@
|
||||
#include "bfa_defs.h"
|
||||
|
||||
#define bfa_ioc_ct_sync_pos(__ioc) \
|
||||
((u32) (1 << bfa_ioc_pcifn(__ioc)))
|
||||
((u32)BIT(bfa_ioc_pcifn(__ioc)))
|
||||
#define BFA_IOC_SYNC_REQD_SH 16
|
||||
#define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
|
||||
#define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
|
||||
|
@ -66,8 +66,9 @@ cmdq_sm_stopped_entry(struct bfa_msgq_cmdq *cmdq)
|
||||
cmdq->offset = 0;
|
||||
cmdq->bytes_to_copy = 0;
|
||||
while (!list_empty(&cmdq->pending_q)) {
|
||||
bfa_q_deq(&cmdq->pending_q, &cmdq_ent);
|
||||
bfa_q_qe_init(&cmdq_ent->qe);
|
||||
cmdq_ent = list_first_entry(&cmdq->pending_q,
|
||||
struct bfa_msgq_cmd_entry, qe);
|
||||
list_del(&cmdq_ent->qe);
|
||||
call_cmdq_ent_cbfn(cmdq_ent, BFA_STATUS_FAILED);
|
||||
}
|
||||
}
|
||||
@ -242,8 +243,8 @@ bfa_msgq_cmdq_ci_update(struct bfa_msgq_cmdq *cmdq, struct bfi_mbmsg *mb)
|
||||
|
||||
/* Walk through pending list to see if the command can be posted */
|
||||
while (!list_empty(&cmdq->pending_q)) {
|
||||
cmd =
|
||||
(struct bfa_msgq_cmd_entry *)bfa_q_first(&cmdq->pending_q);
|
||||
cmd = list_first_entry(&cmdq->pending_q,
|
||||
struct bfa_msgq_cmd_entry, qe);
|
||||
if (ntohs(cmd->msg_hdr->num_entries) <=
|
||||
BFA_MSGQ_FREE_CNT(cmdq)) {
|
||||
list_del(&cmd->qe);
|
||||
@ -615,7 +616,6 @@ bfa_msgq_attach(struct bfa_msgq *msgq, struct bfa_ioc *ioc)
|
||||
bfa_msgq_rspq_attach(&msgq->rspq, msgq);
|
||||
|
||||
bfa_nw_ioc_mbox_regisr(msgq->ioc, BFI_MC_MSGQ, bfa_msgq_isr, msgq);
|
||||
bfa_q_qe_init(&msgq->ioc_notify);
|
||||
bfa_ioc_notify_init(&msgq->ioc_notify, bfa_msgq_notify, msgq);
|
||||
bfa_nw_ioc_notify_register(msgq->ioc, &msgq->ioc_notify);
|
||||
}
|
||||
|
@ -21,8 +21,6 @@
|
||||
|
||||
#include "bfa_defs.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
/* BFI FW image type */
|
||||
#define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */
|
||||
#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
|
||||
@ -36,10 +34,10 @@ struct bfi_mhdr {
|
||||
struct {
|
||||
u8 qid;
|
||||
u8 fn_lpu; /*!< msg destination */
|
||||
} h2i;
|
||||
} __packed h2i;
|
||||
u16 i2htok; /*!< token in msgs to host */
|
||||
} mtag;
|
||||
};
|
||||
} __packed mtag;
|
||||
} __packed;
|
||||
|
||||
#define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
|
||||
#define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1)
|
||||
@ -75,14 +73,14 @@ union bfi_addr_u {
|
||||
struct {
|
||||
u32 addr_lo;
|
||||
u32 addr_hi;
|
||||
} a32;
|
||||
};
|
||||
} __packed a32;
|
||||
} __packed;
|
||||
|
||||
/* Generic DMA addr-len pair. */
|
||||
struct bfi_alen {
|
||||
union bfi_addr_u al_addr; /* DMA addr of buffer */
|
||||
u32 al_len; /* length of buffer */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Large Message structure - 128 Bytes size Msgs
|
||||
@ -96,7 +94,7 @@ struct bfi_alen {
|
||||
struct bfi_mbmsg {
|
||||
struct bfi_mhdr mh;
|
||||
u32 pl[BFI_MBMSG_SZ];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Supported PCI function class codes (personality) */
|
||||
enum bfi_pcifn_class {
|
||||
@ -184,19 +182,19 @@ enum bfi_ioc_i2h_msgs {
|
||||
struct bfi_ioc_getattr_req {
|
||||
struct bfi_mhdr mh;
|
||||
union bfi_addr_u attr_addr;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_ioc_attr {
|
||||
u64 mfg_pwwn; /*!< Mfg port wwn */
|
||||
u64 mfg_nwwn; /*!< Mfg node wwn */
|
||||
mac_t mfg_mac; /*!< Mfg mac */
|
||||
u8 mfg_mac[ETH_ALEN]; /*!< Mfg mac */
|
||||
u8 port_mode; /* enum bfi_port_mode */
|
||||
u8 rsvd_a;
|
||||
u64 pwwn;
|
||||
u64 nwwn;
|
||||
mac_t mac; /*!< PBC or Mfg mac */
|
||||
u8 mac[ETH_ALEN]; /*!< PBC or Mfg mac */
|
||||
u16 rsvd_b;
|
||||
mac_t fcoe_mac;
|
||||
u8 fcoe_mac[ETH_ALEN];
|
||||
u16 rsvd_c;
|
||||
char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
|
||||
u8 pcie_gen;
|
||||
@ -211,14 +209,14 @@ struct bfi_ioc_attr {
|
||||
char optrom_version[BFA_VERSION_LEN];
|
||||
struct bfa_mfg_vpd vpd;
|
||||
u32 card_type; /*!< card type */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_IOC_I2H_GETATTR_REPLY message */
|
||||
struct bfi_ioc_getattr_reply {
|
||||
struct bfi_mhdr mh; /*!< Common msg header */
|
||||
u8 status; /*!< cfg reply status */
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Firmware memory page offsets */
|
||||
#define BFI_IOC_SMEM_PG0_CB (0x40)
|
||||
@ -256,7 +254,7 @@ struct bfi_ioc_fwver {
|
||||
u8 build;
|
||||
u8 rsvd[2];
|
||||
#endif
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_ioc_image_hdr {
|
||||
u32 signature; /*!< constant signature */
|
||||
@ -269,7 +267,7 @@ struct bfi_ioc_image_hdr {
|
||||
u32 rsvd_b[2];
|
||||
struct bfi_ioc_fwver fwver;
|
||||
u32 md5sum[BFI_IOC_MD5SUM_SZ];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
enum bfi_ioc_img_ver_cmp {
|
||||
BFI_IOC_IMG_VER_INCOMP,
|
||||
@ -301,7 +299,7 @@ enum bfi_port_mode {
|
||||
struct bfi_ioc_hbeat {
|
||||
struct bfi_mhdr mh; /*!< common msg header */
|
||||
u32 hb_count; /*!< current heart beat count */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* IOC hardware/firmware state */
|
||||
enum bfi_ioc_state {
|
||||
@ -317,8 +315,6 @@ enum bfi_ioc_state {
|
||||
BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */
|
||||
};
|
||||
|
||||
#define BFI_IOC_ENDIAN_SIG 0x12345678
|
||||
|
||||
enum {
|
||||
BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */
|
||||
BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */
|
||||
@ -337,12 +333,6 @@ enum {
|
||||
BFI_ADAPTER_ ## __prop ## _SH)
|
||||
#define BFI_ADAPTER_SETP(__prop, __val) \
|
||||
((__val) << BFI_ADAPTER_ ## __prop ## _SH)
|
||||
#define BFI_ADAPTER_IS_PROTO(__adap_type) \
|
||||
((__adap_type) & BFI_ADAPTER_PROTO)
|
||||
#define BFI_ADAPTER_IS_TTV(__adap_type) \
|
||||
((__adap_type) & BFI_ADAPTER_TTV)
|
||||
#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
|
||||
((__adap_type) & BFI_ADAPTER_UNSUPP)
|
||||
#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
|
||||
((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
|
||||
BFI_ADAPTER_UNSUPP))
|
||||
@ -353,7 +343,7 @@ struct bfi_ioc_ctrl_req {
|
||||
u16 clscode;
|
||||
u16 rsvd;
|
||||
u32 tv_sec;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
|
||||
struct bfi_ioc_ctrl_reply {
|
||||
@ -362,7 +352,7 @@ struct bfi_ioc_ctrl_reply {
|
||||
u8 port_mode; /*!< enum bfa_mode */
|
||||
u8 cap_bm; /*!< capability bit mask */
|
||||
u8 rsvd;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define BFI_IOC_MSGSZ 8
|
||||
/* H2I Messages */
|
||||
@ -372,14 +362,14 @@ union bfi_ioc_h2i_msg_u {
|
||||
struct bfi_ioc_ctrl_req disable_req;
|
||||
struct bfi_ioc_getattr_req getattr_req;
|
||||
u32 mboxmsg[BFI_IOC_MSGSZ];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* I2H Messages */
|
||||
union bfi_ioc_i2h_msg_u {
|
||||
struct bfi_mhdr mh;
|
||||
struct bfi_ioc_ctrl_reply fw_event;
|
||||
u32 mboxmsg[BFI_IOC_MSGSZ];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* MSGQ
|
||||
@ -408,7 +398,7 @@ struct bfi_msgq_mhdr {
|
||||
u16 num_entries;
|
||||
u8 enet_id;
|
||||
u8 rsvd[1];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \
|
||||
(_mh).msg_class = (_mc); \
|
||||
@ -430,21 +420,21 @@ struct bfi_msgq {
|
||||
union bfi_addr_u addr;
|
||||
u16 q_depth; /* Total num of entries in the queue */
|
||||
u8 rsvd[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
|
||||
struct bfi_msgq_cfg_req {
|
||||
struct bfi_mhdr mh;
|
||||
struct bfi_msgq cmdq;
|
||||
struct bfi_msgq rspq;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_ENET_MSGQ_CFG_RSP */
|
||||
struct bfi_msgq_cfg_rsp {
|
||||
struct bfi_mhdr mh;
|
||||
u8 cmd_status;
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_MSGQ_H2I_DOORBELL */
|
||||
struct bfi_msgq_h2i_db {
|
||||
@ -452,8 +442,8 @@ struct bfi_msgq_h2i_db {
|
||||
union {
|
||||
u16 cmdq_pi;
|
||||
u16 rspq_ci;
|
||||
} idx;
|
||||
};
|
||||
} __packed idx;
|
||||
} __packed;
|
||||
|
||||
/* BFI_MSGQ_I2H_DOORBELL */
|
||||
struct bfi_msgq_i2h_db {
|
||||
@ -461,8 +451,8 @@ struct bfi_msgq_i2h_db {
|
||||
union {
|
||||
u16 rspq_pi;
|
||||
u16 cmdq_ci;
|
||||
} idx;
|
||||
};
|
||||
} __packed idx;
|
||||
} __packed;
|
||||
|
||||
#define BFI_CMD_COPY_SZ 28
|
||||
|
||||
@ -470,14 +460,14 @@ struct bfi_msgq_i2h_db {
|
||||
struct bfi_msgq_h2i_cmdq_copy_rsp {
|
||||
struct bfi_mhdr mh;
|
||||
u8 data[BFI_CMD_COPY_SZ];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_MSGQ_I2H_CMD_COPY_REQ */
|
||||
struct bfi_msgq_i2h_cmdq_copy_req {
|
||||
struct bfi_mhdr mh;
|
||||
u16 offset;
|
||||
u16 len;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* FLASH module specific
|
||||
@ -505,7 +495,7 @@ enum bfi_flash_i2h_msgs {
|
||||
struct bfi_flash_query_req {
|
||||
struct bfi_mhdr mh; /* Common msg header */
|
||||
struct bfi_alen alen;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Flash write request
|
||||
@ -519,7 +509,7 @@ struct bfi_flash_write_req {
|
||||
u8 rsv[2];
|
||||
u32 offset;
|
||||
u32 length;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Flash read request
|
||||
@ -532,7 +522,7 @@ struct bfi_flash_read_req {
|
||||
u32 offset;
|
||||
u32 length;
|
||||
struct bfi_alen alen;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Flash query response
|
||||
@ -540,7 +530,7 @@ struct bfi_flash_read_req {
|
||||
struct bfi_flash_query_rsp {
|
||||
struct bfi_mhdr mh; /* Common msg header */
|
||||
u32 status;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Flash read response
|
||||
@ -552,7 +542,7 @@ struct bfi_flash_read_rsp {
|
||||
u8 rsv[3];
|
||||
u32 status;
|
||||
u32 length;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Flash write response
|
||||
@ -564,8 +554,6 @@ struct bfi_flash_write_rsp {
|
||||
u8 rsv[3];
|
||||
u32 status;
|
||||
u32 length;
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
} __packed;
|
||||
|
||||
#endif /* __BFI_H__ */
|
||||
|
@ -22,8 +22,6 @@
|
||||
#include "bfi.h"
|
||||
#include "bfa_defs_cna.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
enum bfi_port_h2i {
|
||||
BFI_PORT_H2I_ENABLE_REQ = (1),
|
||||
BFI_PORT_H2I_DISABLE_REQ = (2),
|
||||
@ -43,7 +41,7 @@ struct bfi_port_generic_req {
|
||||
struct bfi_mhdr mh; /*!< msg header */
|
||||
u32 msgtag; /*!< msgtag for reply */
|
||||
u32 rsvd;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Generic RSP type */
|
||||
struct bfi_port_generic_rsp {
|
||||
@ -51,13 +49,13 @@ struct bfi_port_generic_rsp {
|
||||
u8 status; /*!< port enable status */
|
||||
u8 rsvd[3];
|
||||
u32 msgtag; /*!< msgtag for reply */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BFI_PORT_H2I_GET_STATS_REQ */
|
||||
struct bfi_port_get_stats_req {
|
||||
struct bfi_mhdr mh; /*!< common msg header */
|
||||
union bfi_addr_u dma_addr;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
union bfi_port_h2i_msg_u {
|
||||
struct bfi_mhdr mh;
|
||||
@ -65,7 +63,7 @@ union bfi_port_h2i_msg_u {
|
||||
struct bfi_port_generic_req disable_req;
|
||||
struct bfi_port_get_stats_req getstats_req;
|
||||
struct bfi_port_generic_req clearstats_req;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
union bfi_port_i2h_msg_u {
|
||||
struct bfi_mhdr mh;
|
||||
@ -73,7 +71,7 @@ union bfi_port_i2h_msg_u {
|
||||
struct bfi_port_generic_rsp disable_rsp;
|
||||
struct bfi_port_generic_rsp getstats_rsp;
|
||||
struct bfi_port_generic_rsp clearstats_rsp;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* @brief Mailbox commands from host to (DCBX/LLDP) firmware */
|
||||
enum bfi_cee_h2i_msgs {
|
||||
@ -97,7 +95,7 @@ enum bfi_cee_i2h_msgs {
|
||||
*/
|
||||
struct bfi_lldp_reset_stats {
|
||||
struct bfi_mhdr mh;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* @brief H2I command structure for resetting the stats.
|
||||
@ -105,7 +103,7 @@ struct bfi_lldp_reset_stats {
|
||||
*/
|
||||
struct bfi_cee_reset_stats {
|
||||
struct bfi_mhdr mh;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* @brief get configuration command from host
|
||||
@ -114,7 +112,7 @@ struct bfi_cee_reset_stats {
|
||||
struct bfi_cee_get_req {
|
||||
struct bfi_mhdr mh;
|
||||
union bfi_addr_u dma_addr;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* @brief reply message from firmware
|
||||
@ -124,7 +122,7 @@ struct bfi_cee_get_rsp {
|
||||
struct bfi_mhdr mh;
|
||||
u8 cmd_status;
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* @brief get configuration command from host
|
||||
@ -133,7 +131,7 @@ struct bfi_cee_get_rsp {
|
||||
struct bfi_cee_stats_req {
|
||||
struct bfi_mhdr mh;
|
||||
union bfi_addr_u dma_addr;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* @brief reply message from firmware
|
||||
@ -143,22 +141,20 @@ struct bfi_cee_stats_rsp {
|
||||
struct bfi_mhdr mh;
|
||||
u8 cmd_status;
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* @brief mailbox command structures from host to firmware */
|
||||
union bfi_cee_h2i_msg_u {
|
||||
struct bfi_mhdr mh;
|
||||
struct bfi_cee_get_req get_req;
|
||||
struct bfi_cee_stats_req stats_req;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* @brief mailbox message structures from firmware to host */
|
||||
union bfi_cee_i2h_msg_u {
|
||||
struct bfi_mhdr mh;
|
||||
struct bfi_cee_get_rsp get_rsp;
|
||||
struct bfi_cee_stats_rsp stats_rsp;
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
} __packed;
|
||||
|
||||
#endif /* __BFI_CNA_H__ */
|
||||
|
@ -36,8 +36,6 @@
|
||||
#include "bfa_defs.h"
|
||||
#include "bfi.h"
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define BFI_ENET_CFG_MAX 32 /* Max resources per PF */
|
||||
|
||||
#define BFI_ENET_TXQ_PRIO_MAX 8
|
||||
@ -59,8 +57,8 @@ union bfi_addr_be_u {
|
||||
struct {
|
||||
u32 addr_hi; /* Most Significant 32-bits */
|
||||
u32 addr_lo; /* Least Significant 32-Bits */
|
||||
} a32;
|
||||
};
|
||||
} __packed a32;
|
||||
} __packed;
|
||||
|
||||
/* T X Q U E U E D E F I N E S */
|
||||
/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
|
||||
@ -70,13 +68,13 @@ union bfi_addr_be_u {
|
||||
#define BFI_ENET_TXQ_WI_EXTENSION (0x104) /* Extension WI */
|
||||
|
||||
/* TxQ Entry Control Flags */
|
||||
#define BFI_ENET_TXQ_WI_CF_FCOE_CRC (1 << 8)
|
||||
#define BFI_ENET_TXQ_WI_CF_IPID_MODE (1 << 5)
|
||||
#define BFI_ENET_TXQ_WI_CF_INS_PRIO (1 << 4)
|
||||
#define BFI_ENET_TXQ_WI_CF_INS_VLAN (1 << 3)
|
||||
#define BFI_ENET_TXQ_WI_CF_UDP_CKSUM (1 << 2)
|
||||
#define BFI_ENET_TXQ_WI_CF_TCP_CKSUM (1 << 1)
|
||||
#define BFI_ENET_TXQ_WI_CF_IP_CKSUM (1 << 0)
|
||||
#define BFI_ENET_TXQ_WI_CF_FCOE_CRC BIT(8)
|
||||
#define BFI_ENET_TXQ_WI_CF_IPID_MODE BIT(5)
|
||||
#define BFI_ENET_TXQ_WI_CF_INS_PRIO BIT(4)
|
||||
#define BFI_ENET_TXQ_WI_CF_INS_VLAN BIT(3)
|
||||
#define BFI_ENET_TXQ_WI_CF_UDP_CKSUM BIT(2)
|
||||
#define BFI_ENET_TXQ_WI_CF_TCP_CKSUM BIT(1)
|
||||
#define BFI_ENET_TXQ_WI_CF_IP_CKSUM BIT(0)
|
||||
|
||||
struct bfi_enet_txq_wi_base {
|
||||
u8 reserved;
|
||||
@ -88,28 +86,28 @@ struct bfi_enet_txq_wi_base {
|
||||
u16 vlan_tag;
|
||||
u16 lso_mss; /* Only 14 LSB are valid */
|
||||
u32 frame_length; /* Only 24 LSB are valid */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_txq_wi_ext {
|
||||
u16 reserved;
|
||||
u16 opcode; /* BFI_ENET_TXQ_WI_EXTENSION */
|
||||
u32 reserved2[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_txq_wi_vector { /* Tx Buffer Descriptor */
|
||||
u16 reserved;
|
||||
u16 length; /* Only 14 LSB are valid */
|
||||
union bfi_addr_be_u addr;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* TxQ Entry Structure */
|
||||
struct bfi_enet_txq_entry {
|
||||
union {
|
||||
struct bfi_enet_txq_wi_base base;
|
||||
struct bfi_enet_txq_wi_ext ext;
|
||||
} wi;
|
||||
} __packed wi;
|
||||
struct bfi_enet_txq_wi_vector vector[BFI_ENET_TXQ_WI_VECT_MAX];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define wi_hdr wi.base
|
||||
#define wi_ext_hdr wi.ext
|
||||
@ -120,36 +118,36 @@ struct bfi_enet_txq_entry {
|
||||
/* R X Q U E U E D E F I N E S */
|
||||
struct bfi_enet_rxq_entry {
|
||||
union bfi_addr_be_u rx_buffer;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* R X C O M P L E T I O N Q U E U E D E F I N E S */
|
||||
/* CQ Entry Flags */
|
||||
#define BFI_ENET_CQ_EF_MAC_ERROR (1 << 0)
|
||||
#define BFI_ENET_CQ_EF_FCS_ERROR (1 << 1)
|
||||
#define BFI_ENET_CQ_EF_TOO_LONG (1 << 2)
|
||||
#define BFI_ENET_CQ_EF_FC_CRC_OK (1 << 3)
|
||||
#define BFI_ENET_CQ_EF_MAC_ERROR BIT(0)
|
||||
#define BFI_ENET_CQ_EF_FCS_ERROR BIT(1)
|
||||
#define BFI_ENET_CQ_EF_TOO_LONG BIT(2)
|
||||
#define BFI_ENET_CQ_EF_FC_CRC_OK BIT(3)
|
||||
|
||||
#define BFI_ENET_CQ_EF_RSVD1 (1 << 4)
|
||||
#define BFI_ENET_CQ_EF_L4_CKSUM_OK (1 << 5)
|
||||
#define BFI_ENET_CQ_EF_L3_CKSUM_OK (1 << 6)
|
||||
#define BFI_ENET_CQ_EF_HDS_HEADER (1 << 7)
|
||||
#define BFI_ENET_CQ_EF_RSVD1 BIT(4)
|
||||
#define BFI_ENET_CQ_EF_L4_CKSUM_OK BIT(5)
|
||||
#define BFI_ENET_CQ_EF_L3_CKSUM_OK BIT(6)
|
||||
#define BFI_ENET_CQ_EF_HDS_HEADER BIT(7)
|
||||
|
||||
#define BFI_ENET_CQ_EF_UDP (1 << 8)
|
||||
#define BFI_ENET_CQ_EF_TCP (1 << 9)
|
||||
#define BFI_ENET_CQ_EF_IP_OPTIONS (1 << 10)
|
||||
#define BFI_ENET_CQ_EF_IPV6 (1 << 11)
|
||||
#define BFI_ENET_CQ_EF_UDP BIT(8)
|
||||
#define BFI_ENET_CQ_EF_TCP BIT(9)
|
||||
#define BFI_ENET_CQ_EF_IP_OPTIONS BIT(10)
|
||||
#define BFI_ENET_CQ_EF_IPV6 BIT(11)
|
||||
|
||||
#define BFI_ENET_CQ_EF_IPV4 (1 << 12)
|
||||
#define BFI_ENET_CQ_EF_VLAN (1 << 13)
|
||||
#define BFI_ENET_CQ_EF_RSS (1 << 14)
|
||||
#define BFI_ENET_CQ_EF_RSVD2 (1 << 15)
|
||||
#define BFI_ENET_CQ_EF_IPV4 BIT(12)
|
||||
#define BFI_ENET_CQ_EF_VLAN BIT(13)
|
||||
#define BFI_ENET_CQ_EF_RSS BIT(14)
|
||||
#define BFI_ENET_CQ_EF_RSVD2 BIT(15)
|
||||
|
||||
#define BFI_ENET_CQ_EF_MCAST_MATCH (1 << 16)
|
||||
#define BFI_ENET_CQ_EF_MCAST (1 << 17)
|
||||
#define BFI_ENET_CQ_EF_BCAST (1 << 18)
|
||||
#define BFI_ENET_CQ_EF_REMOTE (1 << 19)
|
||||
#define BFI_ENET_CQ_EF_MCAST_MATCH BIT(16)
|
||||
#define BFI_ENET_CQ_EF_MCAST BIT(17)
|
||||
#define BFI_ENET_CQ_EF_BCAST BIT(18)
|
||||
#define BFI_ENET_CQ_EF_REMOTE BIT(19)
|
||||
|
||||
#define BFI_ENET_CQ_EF_LOCAL (1 << 20)
|
||||
#define BFI_ENET_CQ_EF_LOCAL BIT(20)
|
||||
|
||||
/* CQ Entry Structure */
|
||||
struct bfi_enet_cq_entry {
|
||||
@ -161,7 +159,7 @@ struct bfi_enet_cq_entry {
|
||||
u8 reserved1;
|
||||
u8 reserved2;
|
||||
u8 rxq_id;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* E N E T C O N T R O L P A T H C O M M A N D S */
|
||||
struct bfi_enet_q {
|
||||
@ -169,23 +167,23 @@ struct bfi_enet_q {
|
||||
union bfi_addr_u first_entry;
|
||||
u16 pages; /* # of pages */
|
||||
u16 page_sz;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_txq {
|
||||
struct bfi_enet_q q;
|
||||
u8 priority;
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_rxq {
|
||||
struct bfi_enet_q q;
|
||||
u16 rx_buffer_size;
|
||||
u16 rsvd;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_cq {
|
||||
struct bfi_enet_q q;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_ib_cfg {
|
||||
u8 int_pkt_dma;
|
||||
@ -198,16 +196,16 @@ struct bfi_enet_ib_cfg {
|
||||
u32 inter_pkt_timeout;
|
||||
u8 inter_pkt_count;
|
||||
u8 rsvd1[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_ib {
|
||||
union bfi_addr_u index_addr;
|
||||
union {
|
||||
u16 msix_index;
|
||||
u16 intx_bitmask;
|
||||
} intr;
|
||||
} __packed intr;
|
||||
u16 rsvd;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* ENET command messages */
|
||||
enum bfi_enet_h2i_msgs {
|
||||
@ -355,7 +353,7 @@ enum bfi_enet_err {
|
||||
*/
|
||||
struct bfi_enet_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Enable/Disable Request
|
||||
*
|
||||
@ -370,7 +368,7 @@ struct bfi_enet_enable_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
u8 enable; /* 1 = enable; 0 = disable */
|
||||
u8 rsvd[3];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Generic Response */
|
||||
struct bfi_enet_rsp {
|
||||
@ -378,7 +376,7 @@ struct bfi_enet_rsp {
|
||||
u8 error; /*!< if error see cmd_offset */
|
||||
u8 rsvd;
|
||||
u16 cmd_offset; /*!< offset to invalid parameter */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* GLOBAL CONFIGURATION */
|
||||
|
||||
@ -387,7 +385,7 @@ struct bfi_enet_rsp {
|
||||
*/
|
||||
struct bfi_enet_attr_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* bfi_enet_attr_rsp is used by:
|
||||
* BFI_ENET_I2H_GET_ATTR_RSP
|
||||
@ -400,7 +398,7 @@ struct bfi_enet_attr_rsp {
|
||||
u32 max_cfg;
|
||||
u32 max_ucmac;
|
||||
u32 rit_size;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Tx Configuration
|
||||
*
|
||||
@ -421,7 +419,7 @@ struct bfi_enet_tx_cfg {
|
||||
u8 apply_vlan_filter;
|
||||
u8 add_to_vswitch;
|
||||
u8 rsvd1[1];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_tx_cfg_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
@ -431,7 +429,7 @@ struct bfi_enet_tx_cfg_req {
|
||||
struct {
|
||||
struct bfi_enet_txq q;
|
||||
struct bfi_enet_ib ib;
|
||||
} q_cfg[BFI_ENET_TXQ_PRIO_MAX];
|
||||
} __packed q_cfg[BFI_ENET_TXQ_PRIO_MAX];
|
||||
|
||||
struct bfi_enet_ib_cfg ib_cfg;
|
||||
|
||||
@ -448,7 +446,7 @@ struct bfi_enet_tx_cfg_rsp {
|
||||
u32 i_dbell; /* PCI base address offset */
|
||||
u8 hw_qid; /* For debugging */
|
||||
u8 rsvd[3];
|
||||
} q_handles[BFI_ENET_TXQ_PRIO_MAX];
|
||||
} __packed q_handles[BFI_ENET_TXQ_PRIO_MAX];
|
||||
};
|
||||
|
||||
/* Rx Configuration
|
||||
@ -481,13 +479,13 @@ struct bfi_enet_rx_cfg {
|
||||
u8 force_offset;
|
||||
u8 type;
|
||||
u8 rsvd1;
|
||||
} hds;
|
||||
} __packed hds;
|
||||
|
||||
u8 multi_buffer;
|
||||
u8 strip_vlan;
|
||||
u8 drop_untagged;
|
||||
u8 rsvd2;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Multicast frames are received on the ql of q-set index zero.
|
||||
@ -504,12 +502,12 @@ struct bfi_enet_rx_cfg_req {
|
||||
struct bfi_enet_rxq qs; /* small/header buffers */
|
||||
struct bfi_enet_cq cq;
|
||||
struct bfi_enet_ib ib;
|
||||
} q_cfg[BFI_ENET_RX_QSET_MAX];
|
||||
} __packed q_cfg[BFI_ENET_RX_QSET_MAX];
|
||||
|
||||
struct bfi_enet_ib_cfg ib_cfg;
|
||||
|
||||
struct bfi_enet_rx_cfg rx_cfg;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_rx_cfg_rsp {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
@ -524,8 +522,8 @@ struct bfi_enet_rx_cfg_rsp {
|
||||
u8 hw_sqid; /* For debugging */
|
||||
u8 hw_cqid; /* For debugging */
|
||||
u8 rsvd;
|
||||
} q_handles[BFI_ENET_RX_QSET_MAX];
|
||||
};
|
||||
} __packed q_handles[BFI_ENET_RX_QSET_MAX];
|
||||
} __packed;
|
||||
|
||||
/* RIT
|
||||
*
|
||||
@ -537,7 +535,7 @@ struct bfi_enet_rit_req {
|
||||
u16 size; /* number of table-entries used */
|
||||
u8 rsvd[2];
|
||||
u8 table[BFI_ENET_RSS_RIT_MAX];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* RSS
|
||||
*
|
||||
@ -556,12 +554,12 @@ struct bfi_enet_rss_cfg {
|
||||
u8 mask;
|
||||
u8 rsvd[2];
|
||||
u32 key[BFI_ENET_RSS_KEY_LEN];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct bfi_enet_rss_cfg_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
struct bfi_enet_rss_cfg cfg;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* MAC Unicast
|
||||
*
|
||||
@ -573,16 +571,16 @@ struct bfi_enet_rss_cfg_req {
|
||||
*/
|
||||
struct bfi_enet_ucast_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
mac_t mac_addr;
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 rsvd[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* MAC Unicast + VLAN */
|
||||
struct bfi_enet_mac_n_vlan_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
u16 vlan_id;
|
||||
mac_t mac_addr;
|
||||
};
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
} __packed;
|
||||
|
||||
/* MAC Multicast
|
||||
*
|
||||
@ -591,9 +589,9 @@ struct bfi_enet_mac_n_vlan_req {
|
||||
*/
|
||||
struct bfi_enet_mcast_add_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
mac_t mac_addr;
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 rsvd[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* bfi_enet_mac_mfilter_add_rsp is used by:
|
||||
* BFI_ENET_I2H_MAC_MCAST_ADD_RSP
|
||||
@ -605,7 +603,7 @@ struct bfi_enet_mcast_add_rsp {
|
||||
u16 cmd_offset;
|
||||
u16 handle;
|
||||
u8 rsvd1[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* bfi_enet_mac_mfilter_del_req is used by:
|
||||
* BFI_ENET_H2I_MAC_MCAST_DEL_REQ
|
||||
@ -614,7 +612,7 @@ struct bfi_enet_mcast_del_req {
|
||||
struct bfi_msgq_mhdr mh;
|
||||
u16 handle;
|
||||
u8 rsvd[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* VLAN
|
||||
*
|
||||
@ -626,7 +624,7 @@ struct bfi_enet_rx_vlan_req {
|
||||
u8 block_idx;
|
||||
u8 rsvd[3];
|
||||
u32 bit_mask[BFI_ENET_VLAN_WORDS_MAX];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* PAUSE
|
||||
*
|
||||
@ -638,7 +636,7 @@ struct bfi_enet_set_pause_req {
|
||||
u8 rsvd[2];
|
||||
u8 tx_pause; /* 1 = enable; 0 = disable */
|
||||
u8 rx_pause; /* 1 = enable; 0 = disable */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* DIAGNOSTICS
|
||||
*
|
||||
@ -650,7 +648,7 @@ struct bfi_enet_diag_lb_req {
|
||||
u8 rsvd[2];
|
||||
u8 mode; /* cable or Serdes */
|
||||
u8 enable; /* 1 = enable; 0 = disable */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* enum for Loopback opmodes */
|
||||
enum {
|
||||
@ -671,14 +669,14 @@ struct bfi_enet_stats_req {
|
||||
u32 rx_enet_mask;
|
||||
u32 tx_enet_mask;
|
||||
union bfi_addr_u host_buffer;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* defines for "stats_mask" above. */
|
||||
#define BFI_ENET_STATS_MAC (1 << 0) /* !< MAC Statistics */
|
||||
#define BFI_ENET_STATS_BPC (1 << 1) /* !< Pause Stats from BPC */
|
||||
#define BFI_ENET_STATS_RAD (1 << 2) /* !< Rx Admission Statistics */
|
||||
#define BFI_ENET_STATS_RX_FC (1 << 3) /* !< Rx FC Stats from RxA */
|
||||
#define BFI_ENET_STATS_TX_FC (1 << 4) /* !< Tx FC Stats from TxA */
|
||||
#define BFI_ENET_STATS_MAC BIT(0) /* !< MAC Statistics */
|
||||
#define BFI_ENET_STATS_BPC BIT(1) /* !< Pause Stats from BPC */
|
||||
#define BFI_ENET_STATS_RAD BIT(2) /* !< Rx Admission Statistics */
|
||||
#define BFI_ENET_STATS_RX_FC BIT(3) /* !< Rx FC Stats from RxA */
|
||||
#define BFI_ENET_STATS_TX_FC BIT(4) /* !< Tx FC Stats from TxA */
|
||||
|
||||
#define BFI_ENET_STATS_ALL 0x1f
|
||||
|
||||
@ -699,7 +697,7 @@ struct bfi_enet_stats_txf {
|
||||
u64 errors;
|
||||
u64 filter_vlan; /* frames filtered due to VLAN */
|
||||
u64 filter_mac_sa; /* frames filtered due to SA check */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* RxF Frame Statistics */
|
||||
struct bfi_enet_stats_rxf {
|
||||
@ -715,7 +713,7 @@ struct bfi_enet_stats_rxf {
|
||||
u64 bcast;
|
||||
u64 bcast_vlan;
|
||||
u64 frame_drops;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* FC Tx Frame Statistics */
|
||||
struct bfi_enet_stats_fc_tx {
|
||||
@ -734,7 +732,7 @@ struct bfi_enet_stats_fc_tx {
|
||||
u64 txf_parity_errors;
|
||||
u64 txf_timeout;
|
||||
u64 txf_fid_parity_errors;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* FC Rx Frame Statistics */
|
||||
struct bfi_enet_stats_fc_rx {
|
||||
@ -749,7 +747,7 @@ struct bfi_enet_stats_fc_rx {
|
||||
u64 rxf_bcast_octets;
|
||||
u64 rxf_bcast;
|
||||
u64 rxf_bcast_vlan;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* RAD Frame Statistics */
|
||||
struct bfi_enet_stats_rad {
|
||||
@ -770,7 +768,7 @@ struct bfi_enet_stats_rad {
|
||||
u64 rx_bcast_vlan;
|
||||
|
||||
u64 rx_drops;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* BPC Tx Registers */
|
||||
struct bfi_enet_stats_bpc {
|
||||
@ -785,7 +783,7 @@ struct bfi_enet_stats_bpc {
|
||||
u64 rx_zero_pause[8]; /*!< Pause cancellation */
|
||||
/*!<Pause initiation rather than retention */
|
||||
u64 rx_first_pause[8];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* MAC Rx Statistics */
|
||||
struct bfi_enet_stats_mac {
|
||||
@ -838,7 +836,7 @@ struct bfi_enet_stats_mac {
|
||||
u64 tx_oversize;
|
||||
u64 tx_undersize;
|
||||
u64 tx_fragments;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
/* Complete statistics, DMAed from fw to host followed by
|
||||
* BFI_ENET_I2H_STATS_GET_RSP
|
||||
@ -852,8 +850,6 @@ struct bfi_enet_stats {
|
||||
struct bfi_enet_stats_fc_tx fc_tx_stats;
|
||||
struct bfi_enet_stats_rxf rxf_stats[BFI_ENET_CFG_MAX];
|
||||
struct bfi_enet_stats_txf txf_stats[BFI_ENET_CFG_MAX];
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
} __packed;
|
||||
|
||||
#endif /* __BFI_ENET_H__ */
|
||||
|
@ -28,36 +28,8 @@ extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
|
||||
|
||||
/* Macros and constants */
|
||||
|
||||
#define BNA_IOC_TIMER_FREQ 200
|
||||
|
||||
/* Log string size */
|
||||
#define BNA_MESSAGE_SIZE 256
|
||||
|
||||
#define bna_is_small_rxq(_id) ((_id) & 0x1)
|
||||
|
||||
#define BNA_MAC_IS_EQUAL(_mac1, _mac2) \
|
||||
(!memcmp((_mac1), (_mac2), sizeof(mac_t)))
|
||||
|
||||
#define BNA_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
|
||||
|
||||
#define BNA_TO_POWER_OF_2(x) \
|
||||
do { \
|
||||
int _shift = 0; \
|
||||
while ((x) && (x) != 1) { \
|
||||
(x) >>= 1; \
|
||||
_shift++; \
|
||||
} \
|
||||
(x) <<= _shift; \
|
||||
} while (0)
|
||||
|
||||
#define BNA_TO_POWER_OF_2_HIGH(x) \
|
||||
do { \
|
||||
int n = 1; \
|
||||
while (n < (x)) \
|
||||
n <<= 1; \
|
||||
(x) = n; \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* input : _addr-> os dma addr in host endian format,
|
||||
* output : _bna_dma_addr-> pointer to hw dma addr
|
||||
@ -80,62 +52,8 @@ do { \
|
||||
| ((ntohl((_bna_dma_addr)->lsb) & 0xffffffff)); \
|
||||
} while (0)
|
||||
|
||||
#define containing_rec(addr, type, field) \
|
||||
((type *)((unsigned char *)(addr) - \
|
||||
(unsigned char *)(&((type *)0)->field)))
|
||||
|
||||
#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
|
||||
|
||||
/* TxQ element is 64 bytes */
|
||||
#define BNA_TXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 6)
|
||||
#define BNA_TXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 6)
|
||||
|
||||
#define BNA_TXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
|
||||
{ \
|
||||
unsigned int page_index; /* index within a page */ \
|
||||
void *page_addr; \
|
||||
page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
|
||||
(_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
|
||||
page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\
|
||||
(_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
|
||||
}
|
||||
|
||||
/* RxQ element is 8 bytes */
|
||||
#define BNA_RXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 3)
|
||||
#define BNA_RXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 3)
|
||||
|
||||
#define BNA_RXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
|
||||
{ \
|
||||
unsigned int page_index; /* index within a page */ \
|
||||
void *page_addr; \
|
||||
page_index = (_qe_idx) & (BNA_RXQ_PAGE_INDEX_MAX - 1); \
|
||||
(_qe_ptr_range) = (BNA_RXQ_PAGE_INDEX_MAX - page_index); \
|
||||
page_addr = (_qpt_ptr)[((_qe_idx) >> \
|
||||
BNA_RXQ_PAGE_INDEX_MAX_SHIFT)]; \
|
||||
(_qe_ptr) = &((struct bna_rxq_entry *)(page_addr))[page_index]; \
|
||||
}
|
||||
|
||||
/* CQ element is 16 bytes */
|
||||
#define BNA_CQ_PAGE_INDEX_MAX (PAGE_SIZE >> 4)
|
||||
#define BNA_CQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 4)
|
||||
|
||||
#define BNA_CQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
|
||||
{ \
|
||||
unsigned int page_index; /* index within a page */ \
|
||||
void *page_addr; \
|
||||
\
|
||||
page_index = (_qe_idx) & (BNA_CQ_PAGE_INDEX_MAX - 1); \
|
||||
(_qe_ptr_range) = (BNA_CQ_PAGE_INDEX_MAX - page_index); \
|
||||
page_addr = (_qpt_ptr)[((_qe_idx) >> \
|
||||
BNA_CQ_PAGE_INDEX_MAX_SHIFT)]; \
|
||||
(_qe_ptr) = &((struct bna_cq_entry *)(page_addr))[page_index];\
|
||||
}
|
||||
|
||||
#define BNA_QE_INDX_2_PTR(_cast, _qe_idx, _q_base) \
|
||||
(&((_cast *)(_q_base))[(_qe_idx)])
|
||||
|
||||
#define BNA_QE_INDX_RANGE(_qe_idx, _q_depth) ((_q_depth) - (_qe_idx))
|
||||
|
||||
#define BNA_QE_INDX_ADD(_qe_idx, _qe_num, _q_depth) \
|
||||
((_qe_idx) = ((_qe_idx) + (_qe_num)) & ((_q_depth) - 1))
|
||||
|
||||
@ -147,31 +65,10 @@ do { \
|
||||
#define BNA_QE_FREE_CNT(_q_ptr, _q_depth) \
|
||||
(((_q_ptr)->consumer_index - (_q_ptr)->producer_index - 1) & \
|
||||
((_q_depth) - 1))
|
||||
|
||||
#define BNA_QE_IN_USE_CNT(_q_ptr, _q_depth) \
|
||||
((((_q_ptr)->producer_index - (_q_ptr)->consumer_index)) & \
|
||||
(_q_depth - 1))
|
||||
|
||||
#define BNA_Q_GET_CI(_q_ptr) ((_q_ptr)->q.consumer_index)
|
||||
|
||||
#define BNA_Q_GET_PI(_q_ptr) ((_q_ptr)->q.producer_index)
|
||||
|
||||
#define BNA_Q_PI_ADD(_q_ptr, _num) \
|
||||
(_q_ptr)->q.producer_index = \
|
||||
(((_q_ptr)->q.producer_index + (_num)) & \
|
||||
((_q_ptr)->q.q_depth - 1))
|
||||
|
||||
#define BNA_Q_CI_ADD(_q_ptr, _num) \
|
||||
(_q_ptr)->q.consumer_index = \
|
||||
(((_q_ptr)->q.consumer_index + (_num)) \
|
||||
& ((_q_ptr)->q.q_depth - 1))
|
||||
|
||||
#define BNA_Q_FREE_COUNT(_q_ptr) \
|
||||
(BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
|
||||
|
||||
#define BNA_Q_IN_USE_COUNT(_q_ptr) \
|
||||
(BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
|
||||
|
||||
#define BNA_LARGE_PKT_SIZE 1000
|
||||
|
||||
#define BNA_UPDATE_PKT_CNT(_pkt, _len) \
|
||||
@ -222,21 +119,6 @@ do { \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define call_rxf_pause_cbfn(rxf) \
|
||||
do { \
|
||||
if ((rxf)->oper_state_cbfn) { \
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *); \
|
||||
struct bnad *cbarg; \
|
||||
cbfn = (rxf)->oper_state_cbfn; \
|
||||
cbarg = (rxf)->oper_state_cbarg; \
|
||||
(rxf)->oper_state_cbfn = NULL; \
|
||||
(rxf)->oper_state_cbarg = NULL; \
|
||||
cbfn(cbarg, rxf->rx); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define call_rxf_resume_cbfn(rxf) call_rxf_pause_cbfn(rxf)
|
||||
|
||||
#define is_xxx_enable(mode, bitmask, xxx) ((bitmask & xxx) && (mode & xxx))
|
||||
|
||||
#define is_xxx_disable(mode, bitmask, xxx) ((bitmask & xxx) && !(mode & xxx))
|
||||
@ -326,28 +208,24 @@ do { \
|
||||
#define bna_rx_rid_mask(_bna) ((_bna)->rx_mod.rid_mask)
|
||||
|
||||
#define bna_tx_from_rid(_bna, _rid, _tx) \
|
||||
do { \
|
||||
struct bna_tx_mod *__tx_mod = &(_bna)->tx_mod; \
|
||||
struct bna_tx *__tx; \
|
||||
struct list_head *qe; \
|
||||
_tx = NULL; \
|
||||
list_for_each(qe, &__tx_mod->tx_active_q) { \
|
||||
__tx = (struct bna_tx *)qe; \
|
||||
if (__tx->rid == (_rid)) { \
|
||||
(_tx) = __tx; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
do { \
|
||||
struct bna_tx_mod *__tx_mod = &(_bna)->tx_mod; \
|
||||
struct bna_tx *__tx; \
|
||||
_tx = NULL; \
|
||||
list_for_each_entry(__tx, &__tx_mod->tx_active_q, qe) { \
|
||||
if (__tx->rid == (_rid)) { \
|
||||
(_tx) = __tx; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define bna_rx_from_rid(_bna, _rid, _rx) \
|
||||
do { \
|
||||
struct bna_rx_mod *__rx_mod = &(_bna)->rx_mod; \
|
||||
struct bna_rx *__rx; \
|
||||
struct list_head *qe; \
|
||||
_rx = NULL; \
|
||||
list_for_each(qe, &__rx_mod->rx_active_q) { \
|
||||
__rx = (struct bna_rx *)qe; \
|
||||
list_for_each_entry(__rx, &__rx_mod->rx_active_q, qe) { \
|
||||
if (__rx->rid == (_rid)) { \
|
||||
(_rx) = __rx; \
|
||||
break; \
|
||||
@ -367,15 +245,12 @@ do { \
|
||||
|
||||
static inline struct bna_mac *bna_mac_find(struct list_head *q, u8 *addr)
|
||||
{
|
||||
struct bna_mac *mac = NULL;
|
||||
struct list_head *qe;
|
||||
list_for_each(qe, q) {
|
||||
if (BNA_MAC_IS_EQUAL(((struct bna_mac *)qe)->addr, addr)) {
|
||||
mac = (struct bna_mac *)qe;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return mac;
|
||||
struct bna_mac *mac;
|
||||
|
||||
list_for_each_entry(mac, q, qe)
|
||||
if (ether_addr_equal(mac->addr, addr))
|
||||
return mac;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define bna_attr(_bna) (&(_bna)->ioceth.attr)
|
||||
@ -401,7 +276,6 @@ void bna_hw_stats_get(struct bna *bna);
|
||||
|
||||
/* APIs for RxF */
|
||||
struct bna_mac *bna_cam_mod_mac_get(struct list_head *head);
|
||||
void bna_cam_mod_mac_put(struct list_head *tail, struct bna_mac *mac);
|
||||
struct bna_mcam_handle *bna_mcam_mod_handle_get(struct bna_mcam_mod *mod);
|
||||
void bna_mcam_mod_handle_put(struct bna_mcam_mod *mcam_mod,
|
||||
struct bna_mcam_handle *handle);
|
||||
@ -489,30 +363,19 @@ void bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo);
|
||||
void bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX]);
|
||||
void bna_rx_dim_update(struct bna_ccb *ccb);
|
||||
enum bna_cb_status
|
||||
bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac);
|
||||
enum bna_cb_status
|
||||
bna_rx_ucast_add(struct bna_rx *rx, u8* ucmac,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
enum bna_cb_status
|
||||
bna_rx_ucast_del(struct bna_rx *rx, u8 *ucmac,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
enum bna_cb_status
|
||||
bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
bna_rx_ucast_listset(struct bna_rx *rx, int count, u8 *uclist);
|
||||
enum bna_cb_status
|
||||
bna_rx_mcast_add(struct bna_rx *rx, u8 *mcmac,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
enum bna_cb_status
|
||||
bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac);
|
||||
void
|
||||
bna_rx_mcast_delall(struct bna_rx *rx,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
bna_rx_mcast_delall(struct bna_rx *rx);
|
||||
enum bna_cb_status
|
||||
bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode rxmode,
|
||||
enum bna_rxmode bitmask,
|
||||
void (*cbfn)(struct bnad *, struct bna_rx *));
|
||||
enum bna_rxmode bitmask);
|
||||
void bna_rx_vlan_add(struct bna_rx *rx, int vlan_id);
|
||||
void bna_rx_vlan_del(struct bna_rx *rx, int vlan_id);
|
||||
void bna_rx_vlanfilter_enable(struct bna_rx *rx);
|
||||
@ -532,11 +395,10 @@ void bna_enet_enable(struct bna_enet *enet);
|
||||
void bna_enet_disable(struct bna_enet *enet, enum bna_cleanup_type type,
|
||||
void (*cbfn)(void *));
|
||||
void bna_enet_pause_config(struct bna_enet *enet,
|
||||
struct bna_pause_config *pause_config,
|
||||
void (*cbfn)(struct bnad *));
|
||||
struct bna_pause_config *pause_config);
|
||||
void bna_enet_mtu_set(struct bna_enet *enet, int mtu,
|
||||
void (*cbfn)(struct bnad *));
|
||||
void bna_enet_perm_mac_get(struct bna_enet *enet, mac_t *mac);
|
||||
void bna_enet_perm_mac_get(struct bna_enet *enet, u8 *mac);
|
||||
|
||||
/* IOCETH */
|
||||
|
||||
|
@ -207,7 +207,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr)
|
||||
for (i = 0; i < BFI_ENET_CFG_MAX; i++) {
|
||||
stats_dst = (u64 *)&(bna->stats.hw_stats.rxf_stats[i]);
|
||||
memset(stats_dst, 0, sizeof(struct bfi_enet_stats_rxf));
|
||||
if (rx_enet_mask & ((u32)(1 << i))) {
|
||||
if (rx_enet_mask & ((u32)BIT(i))) {
|
||||
int k;
|
||||
count = sizeof(struct bfi_enet_stats_rxf) /
|
||||
sizeof(u64);
|
||||
@ -222,7 +222,7 @@ bna_bfi_stats_get_rsp(struct bna *bna, struct bfi_msgq_mhdr *msghdr)
|
||||
for (i = 0; i < BFI_ENET_CFG_MAX; i++) {
|
||||
stats_dst = (u64 *)&(bna->stats.hw_stats.txf_stats[i]);
|
||||
memset(stats_dst, 0, sizeof(struct bfi_enet_stats_txf));
|
||||
if (tx_enet_mask & ((u32)(1 << i))) {
|
||||
if (tx_enet_mask & ((u32)BIT(i))) {
|
||||
int k;
|
||||
count = sizeof(struct bfi_enet_stats_txf) /
|
||||
sizeof(u64);
|
||||
@ -884,16 +884,6 @@ do { \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define call_enet_pause_cbfn(enet) \
|
||||
do { \
|
||||
if ((enet)->pause_cbfn) { \
|
||||
void (*cbfn)(struct bnad *); \
|
||||
cbfn = (enet)->pause_cbfn; \
|
||||
(enet)->pause_cbfn = NULL; \
|
||||
cbfn((enet)->bna->bnad); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define call_enet_mtu_cbfn(enet) \
|
||||
do { \
|
||||
if ((enet)->mtu_cbfn) { \
|
||||
@ -925,7 +915,6 @@ bfa_fsm_state_decl(bna_enet, chld_stop_wait, struct bna_enet,
|
||||
static void
|
||||
bna_enet_sm_stopped_entry(struct bna_enet *enet)
|
||||
{
|
||||
call_enet_pause_cbfn(enet);
|
||||
call_enet_mtu_cbfn(enet);
|
||||
call_enet_stop_cbfn(enet);
|
||||
}
|
||||
@ -947,7 +936,6 @@ bna_enet_sm_stopped(struct bna_enet *enet, enum bna_enet_event event)
|
||||
break;
|
||||
|
||||
case ENET_E_PAUSE_CFG:
|
||||
call_enet_pause_cbfn(enet);
|
||||
break;
|
||||
|
||||
case ENET_E_MTU_CFG:
|
||||
@ -1039,7 +1027,6 @@ bna_enet_sm_started_entry(struct bna_enet *enet)
|
||||
* NOTE: Do not call bna_enet_chld_start() here, since it will be
|
||||
* inadvertently called during cfg_wait->started transition as well
|
||||
*/
|
||||
call_enet_pause_cbfn(enet);
|
||||
call_enet_mtu_cbfn(enet);
|
||||
}
|
||||
|
||||
@ -1211,8 +1198,6 @@ bna_enet_init(struct bna_enet *enet, struct bna *bna)
|
||||
enet->stop_cbfn = NULL;
|
||||
enet->stop_cbarg = NULL;
|
||||
|
||||
enet->pause_cbfn = NULL;
|
||||
|
||||
enet->mtu_cbfn = NULL;
|
||||
|
||||
bfa_fsm_set_state(enet, bna_enet_sm_stopped);
|
||||
@ -1308,13 +1293,10 @@ bna_enet_disable(struct bna_enet *enet, enum bna_cleanup_type type,
|
||||
|
||||
void
|
||||
bna_enet_pause_config(struct bna_enet *enet,
|
||||
struct bna_pause_config *pause_config,
|
||||
void (*cbfn)(struct bnad *))
|
||||
struct bna_pause_config *pause_config)
|
||||
{
|
||||
enet->pause_config = *pause_config;
|
||||
|
||||
enet->pause_cbfn = cbfn;
|
||||
|
||||
bfa_fsm_send_event(enet, ENET_E_PAUSE_CFG);
|
||||
}
|
||||
|
||||
@ -1330,9 +1312,9 @@ bna_enet_mtu_set(struct bna_enet *enet, int mtu,
|
||||
}
|
||||
|
||||
void
|
||||
bna_enet_perm_mac_get(struct bna_enet *enet, mac_t *mac)
|
||||
bna_enet_perm_mac_get(struct bna_enet *enet, u8 *mac)
|
||||
{
|
||||
*mac = bfa_nw_ioc_get_mac(&enet->bna->ioceth.ioc);
|
||||
bfa_nw_ioc_get_mac(&enet->bna->ioceth.ioc, mac);
|
||||
}
|
||||
|
||||
/* IOCETH */
|
||||
@ -1810,17 +1792,13 @@ bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
|
||||
res_info[BNA_MOD_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
|
||||
|
||||
INIT_LIST_HEAD(&ucam_mod->free_q);
|
||||
for (i = 0; i < bna->ioceth.attr.num_ucmac; i++) {
|
||||
bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
|
||||
for (i = 0; i < bna->ioceth.attr.num_ucmac; i++)
|
||||
list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
|
||||
}
|
||||
|
||||
/* A separate queue to allow synchronous setting of a list of MACs */
|
||||
INIT_LIST_HEAD(&ucam_mod->del_q);
|
||||
for (i = i; i < (bna->ioceth.attr.num_ucmac * 2); i++) {
|
||||
bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
|
||||
for (i = i; i < (bna->ioceth.attr.num_ucmac * 2); i++)
|
||||
list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->del_q);
|
||||
}
|
||||
|
||||
ucam_mod->bna = bna;
|
||||
}
|
||||
@ -1828,17 +1806,6 @@ bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
|
||||
static void
|
||||
bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
|
||||
{
|
||||
struct list_head *qe;
|
||||
int i;
|
||||
|
||||
i = 0;
|
||||
list_for_each(qe, &ucam_mod->free_q)
|
||||
i++;
|
||||
|
||||
i = 0;
|
||||
list_for_each(qe, &ucam_mod->del_q)
|
||||
i++;
|
||||
|
||||
ucam_mod->bna = NULL;
|
||||
}
|
||||
|
||||
@ -1852,27 +1819,21 @@ bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
|
||||
res_info[BNA_MOD_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
|
||||
|
||||
INIT_LIST_HEAD(&mcam_mod->free_q);
|
||||
for (i = 0; i < bna->ioceth.attr.num_mcmac; i++) {
|
||||
bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
|
||||
for (i = 0; i < bna->ioceth.attr.num_mcmac; i++)
|
||||
list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
|
||||
}
|
||||
|
||||
mcam_mod->mchandle = (struct bna_mcam_handle *)
|
||||
res_info[BNA_MOD_RES_MEM_T_MCHANDLE_ARRAY].res_u.mem_info.mdl[0].kva;
|
||||
|
||||
INIT_LIST_HEAD(&mcam_mod->free_handle_q);
|
||||
for (i = 0; i < bna->ioceth.attr.num_mcmac; i++) {
|
||||
bfa_q_qe_init(&mcam_mod->mchandle[i].qe);
|
||||
for (i = 0; i < bna->ioceth.attr.num_mcmac; i++)
|
||||
list_add_tail(&mcam_mod->mchandle[i].qe,
|
||||
&mcam_mod->free_handle_q);
|
||||
}
|
||||
&mcam_mod->free_handle_q);
|
||||
|
||||
/* A separate queue to allow synchronous setting of a list of MACs */
|
||||
INIT_LIST_HEAD(&mcam_mod->del_q);
|
||||
for (i = i; i < (bna->ioceth.attr.num_mcmac * 2); i++) {
|
||||
bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
|
||||
for (i = i; i < (bna->ioceth.attr.num_mcmac * 2); i++)
|
||||
list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->del_q);
|
||||
}
|
||||
|
||||
mcam_mod->bna = bna;
|
||||
}
|
||||
@ -1880,18 +1841,6 @@ bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
|
||||
static void
|
||||
bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
|
||||
{
|
||||
struct list_head *qe;
|
||||
int i;
|
||||
|
||||
i = 0;
|
||||
list_for_each(qe, &mcam_mod->free_q) i++;
|
||||
|
||||
i = 0;
|
||||
list_for_each(qe, &mcam_mod->del_q) i++;
|
||||
|
||||
i = 0;
|
||||
list_for_each(qe, &mcam_mod->free_handle_q) i++;
|
||||
|
||||
mcam_mod->bna = NULL;
|
||||
}
|
||||
|
||||
@ -2108,32 +2057,26 @@ bna_num_rxp_set(struct bna *bna, int num_rxp)
|
||||
struct bna_mac *
|
||||
bna_cam_mod_mac_get(struct list_head *head)
|
||||
{
|
||||
struct list_head *qe;
|
||||
struct bna_mac *mac;
|
||||
|
||||
if (list_empty(head))
|
||||
return NULL;
|
||||
mac = list_first_entry_or_null(head, struct bna_mac, qe);
|
||||
if (mac)
|
||||
list_del(&mac->qe);
|
||||
|
||||
bfa_q_deq(head, &qe);
|
||||
return (struct bna_mac *)qe;
|
||||
}
|
||||
|
||||
void
|
||||
bna_cam_mod_mac_put(struct list_head *tail, struct bna_mac *mac)
|
||||
{
|
||||
list_add_tail(&mac->qe, tail);
|
||||
return mac;
|
||||
}
|
||||
|
||||
struct bna_mcam_handle *
|
||||
bna_mcam_mod_handle_get(struct bna_mcam_mod *mcam_mod)
|
||||
{
|
||||
struct list_head *qe;
|
||||
struct bna_mcam_handle *handle;
|
||||
|
||||
if (list_empty(&mcam_mod->free_handle_q))
|
||||
return NULL;
|
||||
handle = list_first_entry_or_null(&mcam_mod->free_handle_q,
|
||||
struct bna_mcam_handle, qe);
|
||||
if (handle)
|
||||
list_del(&handle->qe);
|
||||
|
||||
bfa_q_deq(&mcam_mod->free_handle_q, &qe);
|
||||
|
||||
return (struct bna_mcam_handle *)qe;
|
||||
return handle;
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -213,7 +213,7 @@ do { \
|
||||
* 15 bits (32K) should be large enough to accumulate, anyways, and the max.
|
||||
* acked events to h/w can be (32K + max poll weight) (currently 64).
|
||||
*/
|
||||
#define BNA_IB_MAX_ACK_EVENTS (1 << 15)
|
||||
#define BNA_IB_MAX_ACK_EVENTS BIT(15)
|
||||
|
||||
/* These macros build the data portion of the TxQ/RxQ doorbell */
|
||||
#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
|
||||
@ -282,13 +282,13 @@ do { \
|
||||
#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
|
||||
|
||||
/* TxQ Entry Control Flags */
|
||||
#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
|
||||
#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
|
||||
#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
|
||||
#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
|
||||
#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
|
||||
#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
|
||||
#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
|
||||
#define BNA_TXQ_WI_CF_FCOE_CRC BIT(8)
|
||||
#define BNA_TXQ_WI_CF_IPID_MODE BIT(5)
|
||||
#define BNA_TXQ_WI_CF_INS_PRIO BIT(4)
|
||||
#define BNA_TXQ_WI_CF_INS_VLAN BIT(3)
|
||||
#define BNA_TXQ_WI_CF_UDP_CKSUM BIT(2)
|
||||
#define BNA_TXQ_WI_CF_TCP_CKSUM BIT(1)
|
||||
#define BNA_TXQ_WI_CF_IP_CKSUM BIT(0)
|
||||
|
||||
#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
|
||||
(((_hdr_size) << 10) | ((_offset) & 0x3FF))
|
||||
@ -297,36 +297,36 @@ do { \
|
||||
* Completion Q defines
|
||||
*/
|
||||
/* CQ Entry Flags */
|
||||
#define BNA_CQ_EF_MAC_ERROR (1 << 0)
|
||||
#define BNA_CQ_EF_FCS_ERROR (1 << 1)
|
||||
#define BNA_CQ_EF_TOO_LONG (1 << 2)
|
||||
#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
|
||||
#define BNA_CQ_EF_MAC_ERROR BIT(0)
|
||||
#define BNA_CQ_EF_FCS_ERROR BIT(1)
|
||||
#define BNA_CQ_EF_TOO_LONG BIT(2)
|
||||
#define BNA_CQ_EF_FC_CRC_OK BIT(3)
|
||||
|
||||
#define BNA_CQ_EF_RSVD1 (1 << 4)
|
||||
#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
|
||||
#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
|
||||
#define BNA_CQ_EF_HDS_HEADER (1 << 7)
|
||||
#define BNA_CQ_EF_RSVD1 BIT(4)
|
||||
#define BNA_CQ_EF_L4_CKSUM_OK BIT(5)
|
||||
#define BNA_CQ_EF_L3_CKSUM_OK BIT(6)
|
||||
#define BNA_CQ_EF_HDS_HEADER BIT(7)
|
||||
|
||||
#define BNA_CQ_EF_UDP (1 << 8)
|
||||
#define BNA_CQ_EF_TCP (1 << 9)
|
||||
#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
|
||||
#define BNA_CQ_EF_IPV6 (1 << 11)
|
||||
#define BNA_CQ_EF_UDP BIT(8)
|
||||
#define BNA_CQ_EF_TCP BIT(9)
|
||||
#define BNA_CQ_EF_IP_OPTIONS BIT(10)
|
||||
#define BNA_CQ_EF_IPV6 BIT(11)
|
||||
|
||||
#define BNA_CQ_EF_IPV4 (1 << 12)
|
||||
#define BNA_CQ_EF_VLAN (1 << 13)
|
||||
#define BNA_CQ_EF_RSS (1 << 14)
|
||||
#define BNA_CQ_EF_RSVD2 (1 << 15)
|
||||
#define BNA_CQ_EF_IPV4 BIT(12)
|
||||
#define BNA_CQ_EF_VLAN BIT(13)
|
||||
#define BNA_CQ_EF_RSS BIT(14)
|
||||
#define BNA_CQ_EF_RSVD2 BIT(15)
|
||||
|
||||
#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
|
||||
#define BNA_CQ_EF_MCAST (1 << 17)
|
||||
#define BNA_CQ_EF_BCAST (1 << 18)
|
||||
#define BNA_CQ_EF_REMOTE (1 << 19)
|
||||
#define BNA_CQ_EF_MCAST_MATCH BIT(16)
|
||||
#define BNA_CQ_EF_MCAST BIT(17)
|
||||
#define BNA_CQ_EF_BCAST BIT(18)
|
||||
#define BNA_CQ_EF_REMOTE BIT(19)
|
||||
|
||||
#define BNA_CQ_EF_LOCAL (1 << 20)
|
||||
#define BNA_CQ_EF_LOCAL BIT(20)
|
||||
/* CAT2 ASIC does not use bit 21 as per the SPEC.
|
||||
* Bit 31 is set in every end of frame completion
|
||||
*/
|
||||
#define BNA_CQ_EF_EOP (1 << 31)
|
||||
#define BNA_CQ_EF_EOP BIT(31)
|
||||
|
||||
/* Data structures */
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -135,7 +135,6 @@ enum bna_tx_type {
|
||||
enum bna_tx_flags {
|
||||
BNA_TX_F_ENET_STARTED = 1,
|
||||
BNA_TX_F_ENABLED = 2,
|
||||
BNA_TX_F_PRIO_CHANGED = 4,
|
||||
BNA_TX_F_BW_UPDATED = 8,
|
||||
};
|
||||
|
||||
@ -182,17 +181,11 @@ enum bna_rx_mod_flags {
|
||||
BNA_RX_MOD_F_ENET_LOOPBACK = 2,
|
||||
};
|
||||
|
||||
enum bna_rxf_flags {
|
||||
BNA_RXF_F_PAUSED = 1,
|
||||
};
|
||||
|
||||
enum bna_rxf_event {
|
||||
RXF_E_START = 1,
|
||||
RXF_E_STOP = 2,
|
||||
RXF_E_FAIL = 3,
|
||||
RXF_E_CONFIG = 4,
|
||||
RXF_E_PAUSE = 5,
|
||||
RXF_E_RESUME = 6,
|
||||
RXF_E_FW_RESP = 7,
|
||||
};
|
||||
|
||||
@ -362,9 +355,6 @@ struct bna_enet {
|
||||
void (*stop_cbfn)(void *);
|
||||
void *stop_cbarg;
|
||||
|
||||
/* Callback for bna_enet_pause_config() */
|
||||
void (*pause_cbfn)(struct bnad *);
|
||||
|
||||
/* Callback for bna_enet_mtu_set() */
|
||||
void (*mtu_cbfn)(struct bnad *);
|
||||
|
||||
@ -498,9 +488,6 @@ struct bna_tx {
|
||||
void (*stop_cbfn)(void *arg, struct bna_tx *tx);
|
||||
void *stop_cbarg;
|
||||
|
||||
/* callback for bna_tx_prio_set() */
|
||||
void (*prio_change_cbfn)(struct bnad *bnad, struct bna_tx *tx);
|
||||
|
||||
struct bfa_msgq_cmd_entry msgq_cmd;
|
||||
union {
|
||||
struct bfi_enet_tx_cfg_req cfg_req;
|
||||
@ -676,7 +663,6 @@ struct bna_rx_config {
|
||||
enum bna_rx_type rx_type;
|
||||
int num_paths;
|
||||
enum bna_rxp_type rxp_type;
|
||||
int paused;
|
||||
int coalescing_timeo;
|
||||
/*
|
||||
* Small/Large (or Header/Data) buffer size to be configured
|
||||
@ -721,7 +707,6 @@ struct bna_rxp {
|
||||
/* RxF structure (hardware Rx Function) */
|
||||
struct bna_rxf {
|
||||
bfa_fsm_t fsm;
|
||||
enum bna_rxf_flags flags;
|
||||
|
||||
struct bfa_msgq_cmd_entry msgq_cmd;
|
||||
union {
|
||||
@ -742,10 +727,6 @@ struct bna_rxf {
|
||||
void (*stop_cbfn) (struct bna_rx *rx);
|
||||
struct bna_rx *stop_cbarg;
|
||||
|
||||
/* callback for bna_rx_receive_pause() / bna_rx_receive_resume() */
|
||||
void (*oper_state_cbfn) (struct bnad *bnad, struct bna_rx *rx);
|
||||
struct bnad *oper_state_cbarg;
|
||||
|
||||
/**
|
||||
* callback for:
|
||||
* bna_rxf_ucast_set()
|
||||
|
@ -57,7 +57,8 @@ static u32 bnad_rxqs_per_cq = 2;
|
||||
static u32 bna_id;
|
||||
static struct mutex bnad_list_mutex;
|
||||
static LIST_HEAD(bnad_list);
|
||||
static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
||||
static const u8 bnad_bcast_addr[] __aligned(2) =
|
||||
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
||||
|
||||
/*
|
||||
* Local MACROS
|
||||
@ -724,7 +725,6 @@ next:
|
||||
cmpl->valid = 0;
|
||||
BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
|
||||
}
|
||||
cmpl = &cq[ccb->producer_index];
|
||||
}
|
||||
|
||||
napi_gro_flush(&rx_ctrl->napi, false);
|
||||
@ -875,9 +875,9 @@ bnad_set_netdev_perm_addr(struct bnad *bnad)
|
||||
{
|
||||
struct net_device *netdev = bnad->netdev;
|
||||
|
||||
memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
|
||||
ether_addr_copy(netdev->perm_addr, bnad->perm_addr);
|
||||
if (is_zero_ether_addr(netdev->dev_addr))
|
||||
memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
|
||||
ether_addr_copy(netdev->dev_addr, bnad->perm_addr);
|
||||
}
|
||||
|
||||
/* Control Path Handlers */
|
||||
@ -946,8 +946,7 @@ bnad_cb_ethport_link_status(struct bnad *bnad,
|
||||
if (link_up) {
|
||||
if (!netif_carrier_ok(bnad->netdev)) {
|
||||
uint tx_id, tcb_id;
|
||||
printk(KERN_WARNING "bna: %s link up\n",
|
||||
bnad->netdev->name);
|
||||
netdev_info(bnad->netdev, "link up\n");
|
||||
netif_carrier_on(bnad->netdev);
|
||||
BNAD_UPDATE_CTR(bnad, link_toggle);
|
||||
for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
|
||||
@ -966,10 +965,6 @@ bnad_cb_ethport_link_status(struct bnad *bnad,
|
||||
/*
|
||||
* Force an immediate
|
||||
* Transmit Schedule */
|
||||
printk(KERN_INFO "bna: %s %d "
|
||||
"TXQ_STARTED\n",
|
||||
bnad->netdev->name,
|
||||
txq_id);
|
||||
netif_wake_subqueue(
|
||||
bnad->netdev,
|
||||
txq_id);
|
||||
@ -987,8 +982,7 @@ bnad_cb_ethport_link_status(struct bnad *bnad,
|
||||
}
|
||||
} else {
|
||||
if (netif_carrier_ok(bnad->netdev)) {
|
||||
printk(KERN_WARNING "bna: %s link down\n",
|
||||
bnad->netdev->name);
|
||||
netdev_info(bnad->netdev, "link down\n");
|
||||
netif_carrier_off(bnad->netdev);
|
||||
BNAD_UPDATE_CTR(bnad, link_toggle);
|
||||
}
|
||||
@ -1058,8 +1052,6 @@ bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
|
||||
txq_id = tcb->id;
|
||||
clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
|
||||
netif_stop_subqueue(bnad->netdev, txq_id);
|
||||
printk(KERN_INFO "bna: %s %d TXQ_STOPPED\n",
|
||||
bnad->netdev->name, txq_id);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1082,8 +1074,6 @@ bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
|
||||
BUG_ON(*(tcb->hw_consumer_index) != 0);
|
||||
|
||||
if (netif_carrier_ok(bnad->netdev)) {
|
||||
printk(KERN_INFO "bna: %s %d TXQ_STARTED\n",
|
||||
bnad->netdev->name, txq_id);
|
||||
netif_wake_subqueue(bnad->netdev, txq_id);
|
||||
BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
|
||||
}
|
||||
@ -1094,8 +1084,8 @@ bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
|
||||
* get a 0 MAC address. We try to get the MAC address
|
||||
* again here.
|
||||
*/
|
||||
if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
|
||||
bna_enet_perm_mac_get(&bnad->bna.enet, &bnad->perm_addr);
|
||||
if (is_zero_ether_addr(bnad->perm_addr)) {
|
||||
bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr);
|
||||
bnad_set_netdev_perm_addr(bnad);
|
||||
}
|
||||
}
|
||||
@ -1703,7 +1693,7 @@ bnad_ioc_timeout(unsigned long data)
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_ioc_timeout((void *) &bnad->bna.ioceth.ioc);
|
||||
bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
@ -1714,7 +1704,7 @@ bnad_ioc_hb_check(unsigned long data)
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_ioc_hb_check((void *) &bnad->bna.ioceth.ioc);
|
||||
bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
@ -1725,7 +1715,7 @@ bnad_iocpf_timeout(unsigned long data)
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_iocpf_timeout((void *) &bnad->bna.ioceth.ioc);
|
||||
bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
@ -1736,7 +1726,7 @@ bnad_iocpf_sem_timeout(unsigned long data)
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.ioceth.ioc);
|
||||
bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
|
||||
@ -1862,8 +1852,7 @@ bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
|
||||
struct netdev_hw_addr *mc_addr;
|
||||
|
||||
netdev_for_each_mc_addr(mc_addr, netdev) {
|
||||
memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
|
||||
ETH_ALEN);
|
||||
ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
@ -2137,7 +2126,7 @@ bnad_reinit_rx(struct bnad *bnad)
|
||||
current_err = bnad_setup_rx(bnad, rx_id);
|
||||
if (current_err && !err) {
|
||||
err = current_err;
|
||||
pr_err("RXQ:%u setup failed\n", rx_id);
|
||||
netdev_err(netdev, "RXQ:%u setup failed\n", rx_id);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2349,7 +2338,7 @@ bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
|
||||
if (!bnad->rx_info[0].rx)
|
||||
return 0;
|
||||
|
||||
ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
|
||||
ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr);
|
||||
if (ret != BNA_CB_SUCCESS)
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
@ -2673,8 +2662,9 @@ bnad_enable_msix(struct bnad *bnad)
|
||||
if (ret < 0) {
|
||||
goto intx_mode;
|
||||
} else if (ret < bnad->msix_num) {
|
||||
pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
|
||||
ret, bnad->msix_num);
|
||||
dev_warn(&bnad->pcidev->dev,
|
||||
"%d MSI-X vectors allocated < %d requested\n",
|
||||
ret, bnad->msix_num);
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
/* ret = #of vectors that we got */
|
||||
@ -2696,7 +2686,8 @@ bnad_enable_msix(struct bnad *bnad)
|
||||
return;
|
||||
|
||||
intx_mode:
|
||||
pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
|
||||
dev_warn(&bnad->pcidev->dev,
|
||||
"MSI-X enable failed - operating in INTx mode\n");
|
||||
|
||||
kfree(bnad->msix_table);
|
||||
bnad->msix_table = NULL;
|
||||
@ -2754,7 +2745,7 @@ bnad_open(struct net_device *netdev)
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bna_enet_mtu_set(&bnad->bna.enet,
|
||||
BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
|
||||
bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
|
||||
bna_enet_pause_config(&bnad->bna.enet, &pause_config);
|
||||
bna_enet_enable(&bnad->bna.enet);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
|
||||
@ -3128,7 +3119,7 @@ bnad_set_rx_ucast_fltr(struct bnad *bnad)
|
||||
int entry;
|
||||
|
||||
if (netdev_uc_empty(bnad->netdev)) {
|
||||
bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
|
||||
bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -3141,13 +3132,11 @@ bnad_set_rx_ucast_fltr(struct bnad *bnad)
|
||||
|
||||
entry = 0;
|
||||
netdev_for_each_uc_addr(ha, netdev) {
|
||||
memcpy(&mac_list[entry * ETH_ALEN],
|
||||
&ha->addr[0], ETH_ALEN);
|
||||
ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]);
|
||||
entry++;
|
||||
}
|
||||
|
||||
ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry,
|
||||
mac_list, NULL);
|
||||
ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list);
|
||||
kfree(mac_list);
|
||||
|
||||
if (ret != BNA_CB_SUCCESS)
|
||||
@ -3158,7 +3147,7 @@ bnad_set_rx_ucast_fltr(struct bnad *bnad)
|
||||
/* ucast packets not in UCAM are routed to default function */
|
||||
mode_default:
|
||||
bnad->cfg_flags |= BNAD_CF_DEFAULT;
|
||||
bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL, NULL);
|
||||
bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -3183,12 +3172,11 @@ bnad_set_rx_mcast_fltr(struct bnad *bnad)
|
||||
if (mac_list == NULL)
|
||||
goto mode_allmulti;
|
||||
|
||||
memcpy(&mac_list[0], &bnad_bcast_addr[0], ETH_ALEN);
|
||||
ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]);
|
||||
|
||||
/* copy rest of the MCAST addresses */
|
||||
bnad_netdev_mc_list_get(netdev, mac_list);
|
||||
ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
|
||||
mac_list, NULL);
|
||||
ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list);
|
||||
kfree(mac_list);
|
||||
|
||||
if (ret != BNA_CB_SUCCESS)
|
||||
@ -3198,7 +3186,7 @@ bnad_set_rx_mcast_fltr(struct bnad *bnad)
|
||||
|
||||
mode_allmulti:
|
||||
bnad->cfg_flags |= BNAD_CF_ALLMULTI;
|
||||
bna_rx_mcast_delall(bnad->rx_info[0].rx, NULL);
|
||||
bna_rx_mcast_delall(bnad->rx_info[0].rx);
|
||||
}
|
||||
|
||||
void
|
||||
@ -3237,7 +3225,7 @@ bnad_set_rx_mode(struct net_device *netdev)
|
||||
|
||||
mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
|
||||
BNA_RXMODE_ALLMULTI;
|
||||
bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask, NULL);
|
||||
bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask);
|
||||
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
@ -3248,19 +3236,18 @@ bnad_set_rx_mode(struct net_device *netdev)
|
||||
* in a non-blocking context.
|
||||
*/
|
||||
static int
|
||||
bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
|
||||
bnad_set_mac_address(struct net_device *netdev, void *addr)
|
||||
{
|
||||
int err;
|
||||
struct bnad *bnad = netdev_priv(netdev);
|
||||
struct sockaddr *sa = (struct sockaddr *)mac_addr;
|
||||
struct sockaddr *sa = (struct sockaddr *)addr;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
|
||||
err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
|
||||
|
||||
if (!err)
|
||||
memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
|
||||
ether_addr_copy(netdev->dev_addr, sa->sa_data);
|
||||
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
|
||||
@ -3487,8 +3474,8 @@ bnad_init(struct bnad *bnad,
|
||||
dev_err(&pdev->dev, "ioremap for bar0 failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
|
||||
(unsigned long long) bnad->mmio_len);
|
||||
dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0,
|
||||
(unsigned long long) bnad->mmio_len);
|
||||
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
if (!bnad_msix_disable)
|
||||
@ -3609,13 +3596,10 @@ bnad_pci_probe(struct pci_dev *pdev,
|
||||
struct bfa_pcidev pcidev_info;
|
||||
unsigned long flags;
|
||||
|
||||
pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
|
||||
pdev, pcidev_id, PCI_FUNC(pdev->devfn));
|
||||
|
||||
mutex_lock(&bnad_fwimg_mutex);
|
||||
if (!cna_get_firmware_buf(pdev)) {
|
||||
mutex_unlock(&bnad_fwimg_mutex);
|
||||
pr_warn("Failed to load Firmware Image!\n");
|
||||
dev_err(&pdev->dev, "failed to load firmware image!\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
mutex_unlock(&bnad_fwimg_mutex);
|
||||
@ -3708,8 +3692,7 @@ bnad_pci_probe(struct pci_dev *pdev,
|
||||
*/
|
||||
err = bnad_ioceth_enable(bnad);
|
||||
if (err) {
|
||||
pr_err("BNA: Initialization failed err=%d\n",
|
||||
err);
|
||||
dev_err(&pdev->dev, "initialization failed err=%d\n", err);
|
||||
goto probe_success;
|
||||
}
|
||||
|
||||
@ -3742,7 +3725,7 @@ bnad_pci_probe(struct pci_dev *pdev,
|
||||
|
||||
/* Get the burnt-in mac */
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bna_enet_perm_mac_get(&bna->enet, &bnad->perm_addr);
|
||||
bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr);
|
||||
bnad_set_netdev_perm_addr(bnad);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
|
||||
@ -3751,7 +3734,7 @@ bnad_pci_probe(struct pci_dev *pdev,
|
||||
/* Finally, reguister with net_device layer */
|
||||
err = register_netdev(netdev);
|
||||
if (err) {
|
||||
pr_err("BNA : Registering with netdev failed\n");
|
||||
dev_err(&pdev->dev, "registering net device failed\n");
|
||||
goto probe_uninit;
|
||||
}
|
||||
set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
|
||||
@ -3803,7 +3786,6 @@ bnad_pci_remove(struct pci_dev *pdev)
|
||||
if (!netdev)
|
||||
return;
|
||||
|
||||
pr_info("%s bnad_pci_remove\n", netdev->name);
|
||||
bnad = netdev_priv(netdev);
|
||||
bna = &bnad->bna;
|
||||
|
||||
@ -3864,15 +3846,14 @@ bnad_module_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
pr_info("QLogic BR-series 10G Ethernet driver - version: %s\n",
|
||||
BNAD_VERSION);
|
||||
pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n",
|
||||
BNAD_VERSION);
|
||||
|
||||
bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
|
||||
|
||||
err = pci_register_driver(&bnad_pci_driver);
|
||||
if (err < 0) {
|
||||
pr_err("bna : PCI registration failed in module init "
|
||||
"(%d)\n", err);
|
||||
pr_err("bna: PCI driver registration failed err=%d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
@ -344,7 +344,7 @@ struct bnad {
|
||||
struct bnad_completion bnad_completions;
|
||||
|
||||
/* Burnt in MAC address */
|
||||
mac_t perm_addr;
|
||||
u8 perm_addr[ETH_ALEN];
|
||||
|
||||
struct workqueue_struct *work_q;
|
||||
|
||||
|
@ -76,8 +76,7 @@ bnad_debugfs_open_fwtrc(struct inode *inode, struct file *file)
|
||||
fw_debug->debug_buffer = NULL;
|
||||
kfree(fw_debug);
|
||||
fw_debug = NULL;
|
||||
pr_warn("bnad %s: Failed to collect fwtrc\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed to collect fwtrc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -117,8 +116,7 @@ bnad_debugfs_open_fwsave(struct inode *inode, struct file *file)
|
||||
fw_debug->debug_buffer = NULL;
|
||||
kfree(fw_debug);
|
||||
fw_debug = NULL;
|
||||
pr_warn("bna %s: Failed to collect fwsave\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed to collect fwsave\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -217,8 +215,7 @@ bnad_debugfs_open_drvinfo(struct inode *inode, struct file *file)
|
||||
drv_info->debug_buffer = NULL;
|
||||
kfree(drv_info);
|
||||
drv_info = NULL;
|
||||
pr_warn("bna %s: Failed to collect drvinfo\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed to collect drvinfo\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -321,27 +318,20 @@ bnad_debugfs_write_regrd(struct file *file, const char __user *buf,
|
||||
unsigned long flags;
|
||||
void *kern_buf;
|
||||
|
||||
/* Allocate memory to store the user space buf */
|
||||
kern_buf = kzalloc(nbytes, GFP_KERNEL);
|
||||
if (!kern_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
|
||||
kfree(kern_buf);
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* Copy the user space buf */
|
||||
kern_buf = memdup_user(buf, nbytes);
|
||||
if (IS_ERR(kern_buf))
|
||||
return PTR_ERR(kern_buf);
|
||||
|
||||
rc = sscanf(kern_buf, "%x:%x", &addr, &len);
|
||||
if (rc < 2) {
|
||||
pr_warn("bna %s: Failed to read user buffer\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed to read user buffer\n");
|
||||
kfree(kern_buf);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
kfree(kern_buf);
|
||||
kfree(bnad->regdata);
|
||||
bnad->regdata = NULL;
|
||||
bnad->reglen = 0;
|
||||
|
||||
bnad->regdata = kzalloc(len << 2, GFP_KERNEL);
|
||||
@ -355,8 +345,7 @@ bnad_debugfs_write_regrd(struct file *file, const char __user *buf,
|
||||
/* offset and len sanity check */
|
||||
rc = bna_reg_offset_check(ioc, addr, len);
|
||||
if (rc) {
|
||||
pr_warn("bna %s: Failed reg offset check\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed reg offset check\n");
|
||||
kfree(bnad->regdata);
|
||||
bnad->regdata = NULL;
|
||||
bnad->reglen = 0;
|
||||
@ -388,20 +377,14 @@ bnad_debugfs_write_regwr(struct file *file, const char __user *buf,
|
||||
unsigned long flags;
|
||||
void *kern_buf;
|
||||
|
||||
/* Allocate memory to store the user space buf */
|
||||
kern_buf = kzalloc(nbytes, GFP_KERNEL);
|
||||
if (!kern_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
|
||||
kfree(kern_buf);
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* Copy the user space buf */
|
||||
kern_buf = memdup_user(buf, nbytes);
|
||||
if (IS_ERR(kern_buf))
|
||||
return PTR_ERR(kern_buf);
|
||||
|
||||
rc = sscanf(kern_buf, "%x:%x", &addr, &val);
|
||||
if (rc < 2) {
|
||||
pr_warn("bna %s: Failed to read user buffer\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed to read user buffer\n");
|
||||
kfree(kern_buf);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -412,8 +395,7 @@ bnad_debugfs_write_regwr(struct file *file, const char __user *buf,
|
||||
/* offset and len sanity check */
|
||||
rc = bna_reg_offset_check(ioc, addr, 1);
|
||||
if (rc) {
|
||||
pr_warn("bna %s: Failed reg offset check\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev, "failed reg offset check\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -525,7 +507,8 @@ bnad_debugfs_init(struct bnad *bnad)
|
||||
bna_debugfs_root = debugfs_create_dir("bna", NULL);
|
||||
atomic_set(&bna_debugfs_port_count, 0);
|
||||
if (!bna_debugfs_root) {
|
||||
pr_warn("BNA: debugfs root dir creation failed\n");
|
||||
netdev_warn(bnad->netdev,
|
||||
"debugfs root dir creation failed\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -536,8 +519,8 @@ bnad_debugfs_init(struct bnad *bnad)
|
||||
bnad->port_debugfs_root =
|
||||
debugfs_create_dir(name, bna_debugfs_root);
|
||||
if (!bnad->port_debugfs_root) {
|
||||
pr_warn("bna pci_dev %s: root dir creation failed\n",
|
||||
pci_name(bnad->pcidev));
|
||||
netdev_warn(bnad->netdev,
|
||||
"debugfs root dir creation failed\n");
|
||||
return;
|
||||
}
|
||||
|
||||
@ -552,9 +535,9 @@ bnad_debugfs_init(struct bnad *bnad)
|
||||
bnad,
|
||||
file->fops);
|
||||
if (!bnad->bnad_dentry_files[i]) {
|
||||
pr_warn(
|
||||
"BNA pci_dev:%s: create %s entry failed\n",
|
||||
pci_name(bnad->pcidev), file->name);
|
||||
netdev_warn(bnad->netdev,
|
||||
"create %s entry failed\n",
|
||||
file->name);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -445,13 +445,13 @@ bnad_set_ringparam(struct net_device *netdev,
|
||||
|
||||
if (ringparam->rx_pending < BNAD_MIN_Q_DEPTH ||
|
||||
ringparam->rx_pending > BNAD_MAX_RXQ_DEPTH ||
|
||||
!BNA_POWER_OF_2(ringparam->rx_pending)) {
|
||||
!is_power_of_2(ringparam->rx_pending)) {
|
||||
mutex_unlock(&bnad->conf_mutex);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (ringparam->tx_pending < BNAD_MIN_Q_DEPTH ||
|
||||
ringparam->tx_pending > BNAD_MAX_TXQ_DEPTH ||
|
||||
!BNA_POWER_OF_2(ringparam->tx_pending)) {
|
||||
!is_power_of_2(ringparam->tx_pending)) {
|
||||
mutex_unlock(&bnad->conf_mutex);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -533,7 +533,7 @@ bnad_set_pauseparam(struct net_device *netdev,
|
||||
pause_config.rx_pause = pauseparam->rx_pause;
|
||||
pause_config.tx_pause = pauseparam->tx_pause;
|
||||
spin_lock_irqsave(&bnad->bna_lock, flags);
|
||||
bna_enet_pause_config(&bnad->bna.enet, &pause_config, NULL);
|
||||
bna_enet_pause_config(&bnad->bna.enet, &pause_config);
|
||||
spin_unlock_irqrestore(&bnad->bna_lock, flags);
|
||||
}
|
||||
mutex_unlock(&bnad->conf_mutex);
|
||||
@ -1080,7 +1080,7 @@ bnad_flash_device(struct net_device *netdev, struct ethtool_flash *eflash)
|
||||
|
||||
ret = request_firmware(&fw, eflash->data, &bnad->pcidev->dev);
|
||||
if (ret) {
|
||||
pr_err("BNA: Can't locate firmware %s\n", eflash->data);
|
||||
netdev_err(netdev, "can't load firmware %s\n", eflash->data);
|
||||
goto out;
|
||||
}
|
||||
|
||||
@ -1093,7 +1093,7 @@ bnad_flash_device(struct net_device *netdev, struct ethtool_flash *eflash)
|
||||
bnad->id, (u8 *)fw->data, fw->size, 0,
|
||||
bnad_cb_completion, &fcomp);
|
||||
if (ret != BFA_STATUS_OK) {
|
||||
pr_warn("BNA: Flash update failed with err: %d\n", ret);
|
||||
netdev_warn(netdev, "flash update failed with err=%d\n", ret);
|
||||
ret = -EIO;
|
||||
spin_unlock_irq(&bnad->bna_lock);
|
||||
goto out;
|
||||
@ -1103,8 +1103,9 @@ bnad_flash_device(struct net_device *netdev, struct ethtool_flash *eflash)
|
||||
wait_for_completion(&fcomp.comp);
|
||||
if (fcomp.comp_status != BFA_STATUS_OK) {
|
||||
ret = -EIO;
|
||||
pr_warn("BNA: Firmware image update to flash failed with: %d\n",
|
||||
fcomp.comp_status);
|
||||
netdev_warn(netdev,
|
||||
"firmware image update failed with err=%d\n",
|
||||
fcomp.comp_status);
|
||||
}
|
||||
out:
|
||||
release_firmware(fw);
|
||||
|
@ -42,66 +42,4 @@ extern char bfa_version[];
|
||||
#define CNA_FW_FILE_CT2 "ct2fw-3.2.5.1.bin"
|
||||
#define FC_SYMNAME_MAX 256 /*!< max name server symbolic name size */
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct mac { u8 mac[ETH_ALEN]; } mac_t;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#define bfa_q_first(_q) ((void *)(((struct list_head *) (_q))->next))
|
||||
#define bfa_q_next(_qe) (((struct list_head *) (_qe))->next)
|
||||
#define bfa_q_prev(_qe) (((struct list_head *) (_qe))->prev)
|
||||
|
||||
/*
|
||||
* bfa_q_qe_init - to initialize a queue element
|
||||
*/
|
||||
#define bfa_q_qe_init(_qe) { \
|
||||
bfa_q_next(_qe) = (struct list_head *) NULL; \
|
||||
bfa_q_prev(_qe) = (struct list_head *) NULL; \
|
||||
}
|
||||
|
||||
/*
|
||||
* bfa_q_deq - dequeue an element from head of the queue
|
||||
*/
|
||||
#define bfa_q_deq(_q, _qe) { \
|
||||
if (!list_empty(_q)) { \
|
||||
(*((struct list_head **) (_qe))) = bfa_q_next(_q); \
|
||||
bfa_q_prev(bfa_q_next(*((struct list_head **) _qe))) = \
|
||||
(struct list_head *) (_q); \
|
||||
bfa_q_next(_q) = bfa_q_next(*((struct list_head **) _qe)); \
|
||||
bfa_q_qe_init(*((struct list_head **) _qe)); \
|
||||
} else { \
|
||||
*((struct list_head **)(_qe)) = NULL; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* bfa_q_deq_tail - dequeue an element from tail of the queue
|
||||
*/
|
||||
#define bfa_q_deq_tail(_q, _qe) { \
|
||||
if (!list_empty(_q)) { \
|
||||
*((struct list_head **) (_qe)) = bfa_q_prev(_q); \
|
||||
bfa_q_next(bfa_q_prev(*((struct list_head **) _qe))) = \
|
||||
(struct list_head *) (_q); \
|
||||
bfa_q_prev(_q) = bfa_q_prev(*(struct list_head **) _qe);\
|
||||
bfa_q_qe_init(*((struct list_head **) _qe)); \
|
||||
} else { \
|
||||
*((struct list_head **) (_qe)) = (struct list_head *) NULL; \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* bfa_add_tail_head - enqueue an element at the head of queue
|
||||
*/
|
||||
#define bfa_q_enq_head(_q, _qe) { \
|
||||
if (!(bfa_q_next(_qe) == NULL) && (bfa_q_prev(_qe) == NULL)) \
|
||||
pr_err("Assertion failure: %s:%d: %d", \
|
||||
__FILE__, __LINE__, \
|
||||
(bfa_q_next(_qe) == NULL) && (bfa_q_prev(_qe) == NULL));\
|
||||
bfa_q_next(_qe) = bfa_q_next(_q); \
|
||||
bfa_q_prev(_qe) = (struct list_head *) (_q); \
|
||||
bfa_q_prev(bfa_q_next(_q)) = (struct list_head *) (_qe); \
|
||||
bfa_q_next(_q) = (struct list_head *) (_qe); \
|
||||
}
|
||||
|
||||
#endif /* __CNA_H__ */
|
||||
|
@ -33,7 +33,7 @@ cna_read_firmware(struct pci_dev *pdev, u32 **bfi_image,
|
||||
u32 n;
|
||||
|
||||
if (request_firmware(&fw, fw_name, &pdev->dev)) {
|
||||
pr_alert("Can't locate firmware %s\n", fw_name);
|
||||
dev_alert(&pdev->dev, "can't load firmware %s\n", fw_name);
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user