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ARM: 8942/1: Revert "8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

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This reverts commit e17b1af96b, which is
no longer necessary now that the v7 specific routines take care not to
issue CP15 barrier instructions before they are enabled in SCTLR.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Ard Biesheuvel 2019-11-22 13:01:17 +01:00 committed by Russell King
parent 8239fc7755
commit cf17a1e3aa
1 changed files with 1 additions and 15 deletions
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16
arch/arm/boot/compressed/head.S
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@ -1460,21 +1460,7 @@ ENTRY(efi_stub_entry)
@ Preserve return value of efi_entry() in r4 @ Preserve return value of efi_entry() in r4
mov r4, r0 mov r4, r0
bl cache_clean_flush
@ our cache maintenance code relies on CP15 barrier instructions
@ but since we arrived here with the MMU and caches configured
@ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
@ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
@ the enable path will be executed on v7+ only.
mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
tst r1, #(1 << 5) @ CP15BEN bit set?
bne 0f
orr r1, r1, #(1 << 5) @ CP15 barrier instructions
mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
ARM( .inst 0xf57ff06f @ v7+ isb )
THUMB( isb )
0: bl cache_clean_flush
bl cache_off bl cache_off
@ Set parameters for booting zImage according to boot protocol @ Set parameters for booting zImage according to boot protocol