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clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -73,7 +73,7 @@ static struct clk *clks[IMX6UL_CLK_END];
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static struct clk_onecell_data clk_data;
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static int const clks_init_on[] __initconst = {
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IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
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IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
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IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
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IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
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};
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@ -341,9 +341,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26);
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clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
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clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
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if (clk_on_imx6ul())
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clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
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else if (clk_on_imx6ull())
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if (clk_on_imx6ull())
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clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
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/* CCGR1 */
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@ -482,6 +480,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
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clk_prepare_enable(clks[clks_init_on[i]]);
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if (clk_on_imx6ull())
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clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]);
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if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
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clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]);
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clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]);
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