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accel/habanalabs: add cpld ts cpld_timestamp cpucp

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Add cpld_timestamp field to cpucp_info structure and return cpld
timestamp as part of cpld version

Signed-off-by: Vitaly Margolin <vmargolin@habana.ai>
Reviewed-by: Ofir Bitton <obitton@habana.ai>
Signed-off-by: Ofir Bitton <obitton@habana.ai>
This commit is contained in:
Vitaly Margolin 2024-05-27 17:25:37 +03:00 committed by Ofir Bitton
parent 3d613b0cb5
commit cebb64f933
2 changed files with 5 additions and 3 deletions
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5
drivers/accel/habanalabs/common/sysfs.c
View File

@ -142,8 +142,9 @@ static ssize_t cpld_ver_show(struct device *dev, struct device_attribute *attr,
{
struct hl_device *hdev = dev_get_drvdata(dev);
return sprintf(buf, "0x%08x\n",
le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_version));
return sprintf(buf, "0x%08x%08x\n",
le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_timestamp),
le32_to_cpu(hdev->asic_prop.cpucp_info.cpld_version));
}
static ssize_t cpucp_kernel_ver_show(struct device *dev,

3
include/linux/habanalabs/cpucp_if.h
View File

@ -1146,6 +1146,7 @@ struct cpucp_security_info {
* (0 = fully functional, 1 = lower-half is not functional,
* 2 = upper-half is not functional)
* @sec_info: security information
* @cpld_timestamp: CPLD programmed F/W timestamp.
* @pll_map: Bit map of supported PLLs for current ASIC version.
* @mme_binning_mask: MME binning mask,
* bits [0:6] <==> dcore0 mme fma
@ -1193,7 +1194,7 @@ struct cpucp_info {
__u8 substrate_version;
__u8 eq_health_check_supported;
struct cpucp_security_info sec_info;
__le32 reserved2;
__le32 cpld_timestamp;
__u8 pll_map[PLL_MAP_LEN];
__le64 mme_binning_mask;
__u8 fw_os_version[VERSION_MAX_LEN];