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ARCv2: Implement atomic64 based on LLOCKD/SCONDD instructions
ARCv2 ISA provides 64-bit exclusive load/stores so use them to implement the 64-bit atomics and elide the spinlock based generic 64-bit atomics boot tested with atomic64 self-test (and GOD bless the person who wrote them, I realized my inline assmebly is sloppy as hell) Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
26c01c49d5
commit
ce6365270e
@ -13,7 +13,7 @@ config ARC
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select CLKSRC_OF
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select CLONE_BACKWARDS
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select COMMON_CLK
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select GENERIC_ATOMIC64
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select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
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select GENERIC_CLOCKEVENTS
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select GENERIC_FIND_FIRST_BIT
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# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
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@ -20,6 +20,7 @@
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define ATOMIC_INIT(i) { (i) }
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#ifdef CONFIG_ARC_HAS_LLSC
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@ -343,10 +344,266 @@ ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
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#define atomic_add_negative(i, v) (atomic_add_return(i, v) < 0)
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#define ATOMIC_INIT(i) { (i) }
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#ifdef CONFIG_GENERIC_ATOMIC64
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#include <asm-generic/atomic64.h>
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#endif
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#else /* Kconfig ensures this is only enabled with needed h/w assist */
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/*
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* ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
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* - The address HAS to be 64-bit aligned
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* - There are 2 semantics involved here:
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* = exclusive implies no interim update between load/store to same addr
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* = both words are observed/updated together: this is guaranteed even
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* for regular 64-bit load (LDD) / store (STD). Thus atomic64_set()
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* is NOT required to use LLOCKD+SCONDD, STD suffices
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*/
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typedef struct {
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aligned_u64 counter;
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} atomic64_t;
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#define ATOMIC64_INIT(a) { (a) }
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static inline long long atomic64_read(const atomic64_t *v)
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{
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unsigned long long val;
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__asm__ __volatile__(
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" ldd %0, [%1] \n"
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: "=r"(val)
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: "r"(&v->counter));
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return val;
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}
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static inline void atomic64_set(atomic64_t *v, long long a)
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{
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/*
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* This could have been a simple assignment in "C" but would need
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* explicit volatile. Otherwise gcc optimizers could elide the store
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* which borked atomic64 self-test
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* In the inline asm version, memory clobber needed for exact same
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* reason, to tell gcc about the store.
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*
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* This however is not needed for sibling atomic64_add() etc since both
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* load/store are explicitly done in inline asm. As long as API is used
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* for each access, gcc has no way to optimize away any load/store
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*/
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__asm__ __volatile__(
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" std %0, [%1] \n"
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:
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: "r"(a), "r"(&v->counter)
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: "memory");
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}
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#define ATOMIC64_OP(op, op1, op2) \
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static inline void atomic64_##op(long long a, atomic64_t *v) \
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{ \
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unsigned long long val; \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%1] \n" \
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" " #op1 " %L0, %L0, %L2 \n" \
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" " #op2 " %H0, %H0, %H2 \n" \
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" scondd %0, [%1] \n" \
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" bnz 1b \n" \
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: "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); \
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} \
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#define ATOMIC64_OP_RETURN(op, op1, op2) \
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static inline long long atomic64_##op##_return(long long a, atomic64_t *v) \
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{ \
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unsigned long long val; \
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\
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%1] \n" \
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" " #op1 " %L0, %L0, %L2 \n" \
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" " #op2 " %H0, %H0, %H2 \n" \
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" scondd %0, [%1] \n" \
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" bnz 1b \n" \
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: [val] "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); /* memory clobber comes from smp_mb() */ \
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\
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smp_mb(); \
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\
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return val; \
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}
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#define ATOMIC64_FETCH_OP(op, op1, op2) \
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static inline long long atomic64_fetch_##op(long long a, atomic64_t *v) \
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{ \
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unsigned long long val, orig; \
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\
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: \n" \
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" llockd %0, [%2] \n" \
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" " #op1 " %L1, %L0, %L3 \n" \
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" " #op2 " %H1, %H0, %H3 \n" \
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" scondd %1, [%2] \n" \
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" bnz 1b \n" \
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: "=&r"(orig), "=&r"(val) \
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: "r"(&v->counter), "ir"(a) \
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: "cc"); /* memory clobber comes from smp_mb() */ \
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\
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smp_mb(); \
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\
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return orig; \
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}
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#define ATOMIC64_OPS(op, op1, op2) \
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ATOMIC64_OP(op, op1, op2) \
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ATOMIC64_OP_RETURN(op, op1, op2) \
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ATOMIC64_FETCH_OP(op, op1, op2)
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#define atomic64_andnot atomic64_andnot
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ATOMIC64_OPS(add, add.f, adc)
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ATOMIC64_OPS(sub, sub.f, sbc)
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ATOMIC64_OPS(and, and, and)
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ATOMIC64_OPS(andnot, bic, bic)
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ATOMIC64_OPS(or, or, or)
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ATOMIC64_OPS(xor, xor, xor)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static inline long long
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atomic64_cmpxchg(atomic64_t *ptr, long long expected, long long new)
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{
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long long prev;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" brne %L0, %L2, 2f \n"
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" brne %H0, %H2, 2f \n"
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" scondd %3, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev)
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: "r"(ptr), "ir"(expected), "r"(new)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return prev;
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}
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static inline long long atomic64_xchg(atomic64_t *ptr, long long new)
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{
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long long prev;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" scondd %2, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev)
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: "r"(ptr), "r"(new)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return prev;
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}
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/**
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* atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic64_t
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*
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static inline long long atomic64_dec_if_positive(atomic64_t *v)
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{
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long long val;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%1] \n"
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" sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
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" sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
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" brlt %H0, 0, 2f \n"
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" scondd %0, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(val)
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: "r"(&v->counter)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return val;
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}
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/**
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* atomic64_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* if (v != u) { v += a; ret = 1} else {ret = 0}
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* Returns 1 iff @v was not @u (i.e. if add actually happened)
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*/
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static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
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{
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long long val;
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int op_done;
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smp_mb();
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__asm__ __volatile__(
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"1: llockd %0, [%2] \n"
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" mov %1, 1 \n"
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" brne %L0, %L4, 2f # continue to add since v != u \n"
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" breq.d %H0, %H4, 3f # return since v == u \n"
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" mov %1, 0 \n"
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"2: \n"
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" add.f %L0, %L0, %L3 \n"
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" adc %H0, %H0, %H3 \n"
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" scondd %0, [%2] \n"
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" bnz 1b \n"
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"3: \n"
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: "=&r"(val), "=&r" (op_done)
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: "r"(&v->counter), "r"(a), "r"(u)
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: "cc"); /* memory clobber comes from smp_mb() */
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smp_mb();
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return op_done;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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#define atomic64_inc(v) atomic64_add(1LL, (v))
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#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec(v) atomic64_sub(1LL, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
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#endif /* !CONFIG_GENERIC_ATOMIC64 */
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#endif /* !__ASSEMBLY__ */
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#endif
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