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fm10k: don't stop reset due to FM10K_ERR_REQUESTS_PENDING
Don't report FM10K_ERR_REQUESTS_PENDING when we fail to disable queues within the timeout. This can occur due to a hardware Tx hang, or when the switch ethernet fabric is resetting while we are transmitting traffic. It can sometimes take up to 500ms before the Tx DMA engine gives up. Instead, just skip the DMA engine check and perform a data-path reset anyways. Add a statistic counter to keep track of the number of resets occurring while we have pending DMA on the rings. In order to prevent having to re-assign err to 0, re-order the last few items of the reset_hw_pf function so that we don't perform "return err" at the end. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Krishneil Singh <Krishneil.k.singh@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -76,6 +76,8 @@ static const struct fm10k_stats fm10k_gstrings_global_stats[] = {
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FM10K_STAT("mac_rules_used", hw.swapi.mac.used),
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FM10K_STAT("mac_rules_avail", hw.swapi.mac.avail),
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FM10K_STAT("reset_while_pending", hw.mac.reset_while_pending),
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FM10K_STAT("tx_hang_count", tx_timeout_count),
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};
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@ -51,8 +51,12 @@ static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
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/* shut down all rings */
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err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
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if (err)
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if (err == FM10K_ERR_REQUESTS_PENDING) {
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hw->mac.reset_while_pending++;
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goto force_reset;
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} else if (err) {
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return err;
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}
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/* Verify that DMA is no longer active */
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reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
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@ -62,27 +66,27 @@ static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
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/* verify the switch is ready for reset */
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reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
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if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))
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goto out;
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return FM10K_ERR_DMA_PENDING;
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force_reset:
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/* Inititate data path reset */
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reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
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reg = FM10K_DMA_CTRL_DATAPATH_RESET;
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fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
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/* Flush write and allow 100us for reset to complete */
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fm10k_write_flush(hw);
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udelay(FM10K_RESET_TIMEOUT);
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/* Verify we made it out of reset */
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reg = fm10k_read_reg(hw, FM10K_IP);
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if (!(reg & FM10K_IP_NOTINRESET))
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err = FM10K_ERR_RESET_FAILED;
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/* Reset mailbox global interrupts */
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reg = FM10K_MBX_GLOBAL_REQ_INTERRUPT | FM10K_MBX_GLOBAL_ACK_INTERRUPT;
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fm10k_write_reg(hw, FM10K_GMBX, reg);
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out:
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return err;
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/* Verify we made it out of reset */
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reg = fm10k_read_reg(hw, FM10K_IP);
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if (!(reg & FM10K_IP_NOTINRESET))
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return FM10K_ERR_RESET_FAILED;
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return 0;
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}
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/**
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@ -562,6 +562,7 @@ struct fm10k_mac_info {
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bool tx_ready;
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u32 dglort_map;
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u8 itr_scale;
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u64 reset_while_pending;
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};
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struct fm10k_swapi_table_info {
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@ -34,7 +34,7 @@ static s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
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/* we need to disable the queues before taking further steps */
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err = fm10k_stop_hw_generic(hw);
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if (err)
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if (err && err != FM10K_ERR_REQUESTS_PENDING)
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return err;
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/* If permanent address is set then we need to restore it */
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@ -67,7 +67,7 @@ static s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
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fm10k_write_reg(hw, FM10K_TDLEN(i), tdlen);
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}
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return 0;
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return err;
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}
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/**
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@ -83,7 +83,9 @@ static s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)
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/* shut down queues we own and reset DMA configuration */
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err = fm10k_stop_hw_vf(hw);
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if (err)
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if (err == FM10K_ERR_REQUESTS_PENDING)
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hw->mac.reset_while_pending++;
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else if (err)
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return err;
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/* Inititate VF reset */
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@ -96,9 +98,9 @@ static s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)
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/* Clear reset bit and verify it was cleared */
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fm10k_write_reg(hw, FM10K_VFCTRL, 0);
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if (fm10k_read_reg(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)
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err = FM10K_ERR_RESET_FAILED;
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return FM10K_ERR_RESET_FAILED;
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return err;
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return 0;
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}
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/**
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