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ASoC: Allow configuration of WM8904 GPIO pin functions
Provide platform data allowing the configuration of the GPIO pins on the WM8904 to be selected, allowing alternate functions to be enabled. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
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Mark Brown
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7245387e36
commit
cdce4e9ba7
@ -15,8 +15,76 @@
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#ifndef __MFD_WM8994_PDATA_H__
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#ifndef __MFD_WM8994_PDATA_H__
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#define __MFD_WM8994_PDATA_H__
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#define __MFD_WM8994_PDATA_H__
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#define WM8904_DRC_REGS 4
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/* Used to enable configuration of a GPIO to all zeros */
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#define WM8904_EQ_REGS 25
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#define WM8904_GPIO_NO_CONFIG 0x8000
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/*
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* R121 (0x79) - GPIO Control 1
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*/
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#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
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#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
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#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
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#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
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#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
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/*
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* R122 (0x7A) - GPIO Control 2
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*/
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#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
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#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
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#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
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#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
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#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
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/*
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* R123 (0x7B) - GPIO Control 3
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*/
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#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
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#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
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#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
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#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
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#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
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/*
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* R124 (0x7C) - GPIO Control 4
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*/
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#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
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#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
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#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
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#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
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#define WM8904_GPIO_REGS 4
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#define WM8904_DRC_REGS 4
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#define WM8904_EQ_REGS 25
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/**
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/**
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* DRC configurations are specified with a label and a set of register
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* DRC configurations are specified with a label and a set of register
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@ -52,6 +120,8 @@ struct wm8904_pdata {
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int num_retune_mobile_cfgs;
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int num_retune_mobile_cfgs;
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struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
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struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
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u32 gpio_cfg[WM8904_GPIO_REGS];
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};
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};
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#endif
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#endif
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@ -2425,6 +2425,7 @@ EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904);
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static int wm8904_register(struct wm8904_priv *wm8904,
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static int wm8904_register(struct wm8904_priv *wm8904,
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enum snd_soc_control_type control)
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enum snd_soc_control_type control)
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{
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{
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struct wm8904_pdata *pdata = wm8904->pdata;
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int ret;
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int ret;
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struct snd_soc_codec *codec = &wm8904->codec;
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struct snd_soc_codec *codec = &wm8904->codec;
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int i;
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int i;
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@ -2530,6 +2531,17 @@ static int wm8904_register(struct wm8904_priv *wm8904,
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WM8904_LINEOUTRZC;
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WM8904_LINEOUTRZC;
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wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
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wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
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/* Apply configuration from the platform data. */
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if (wm8904->pdata) {
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for (i = 0; i < WM8904_GPIO_REGS; i++) {
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if (!pdata->gpio_cfg[i])
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continue;
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wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i]
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= pdata->gpio_cfg[i] & 0xffff;
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}
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}
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/* Set Class W by default - this will be managed by the Class
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/* Set Class W by default - this will be managed by the Class
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* G widget at runtime where bypass paths are available.
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* G widget at runtime where bypass paths are available.
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*/
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*/
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@ -1199,70 +1199,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8904;
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#define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
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#define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
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#define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
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#define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
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/*
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* R121 (0x79) - GPIO Control 1
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*/
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#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
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#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
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#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
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#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
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#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
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#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
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#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
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/*
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* R122 (0x7A) - GPIO Control 2
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*/
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#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
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#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
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#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
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#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
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#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
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#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
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#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
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/*
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* R123 (0x7B) - GPIO Control 3
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*/
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#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
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#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
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#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
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#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
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#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
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#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
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#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
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/*
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* R124 (0x7C) - GPIO Control 4
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*/
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#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
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#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
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#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
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#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
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#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
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#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
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#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
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/*
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/*
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* R126 (0x7E) - Digital Pulls
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* R126 (0x7E) - Digital Pulls
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*/
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*/
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