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https://github.com/torvalds/linux.git
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drm/nv50-nvc0: initialise display sync channels
Also imports a couple of helper functions that'll be used to implement page flipping in the following commits.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
45c4e0aae9
commit
cdccc70eff
@ -73,6 +73,8 @@ enum {
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NvImageBlit = 0x8000000d,
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NvSw = 0x8000000e,
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NvSema = 0x8000000f,
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NvEvoSema0 = 0x80000010,
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NvEvoSema1 = 0x80000011,
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/* G80+ display objects */
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NvEvoVRAM = 0x01000000,
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@ -36,6 +36,7 @@
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#include "nouveau_drm.h"
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#include "nouveau_ramht.h"
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#include "nouveau_vm.h"
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#include "nv50_display.h"
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struct nouveau_gpuobj_method {
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struct list_head head;
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@ -782,7 +783,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *vram = NULL, *tt = NULL;
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int ret;
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int ret, i;
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NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
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@ -847,6 +848,25 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
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nouveau_gpuobj_ref(NULL, &ramht);
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if (ret)
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return ret;
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/* dma objects for display sync channel semaphore blocks */
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for (i = 0; i < 2; i++) {
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struct nouveau_gpuobj *sem = NULL;
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struct nv50_display_crtc *dispc =
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&nv50_display(dev)->crtc[i];
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u64 offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;
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ret = nouveau_gpuobj_dma_new(chan, 0x3d, offset, 0xfff,
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NV_MEM_ACCESS_RW,
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NV_MEM_TARGET_VRAM, &sem);
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if (ret)
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return ret;
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ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, sem);
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nouveau_gpuobj_ref(NULL, &sem);
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if (ret)
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return ret;
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}
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}
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/* VRAM ctxdma */
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@ -178,7 +178,7 @@ nv50_display_init(struct drm_device *dev)
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nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
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ret = RING_SPACE(evo, 11);
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ret = RING_SPACE(evo, 15);
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if (ret)
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return ret;
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BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
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@ -192,6 +192,11 @@ nv50_display_init(struct drm_device *dev)
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OUT_RING(evo, 0);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
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OUT_RING(evo, 0);
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/* required to make display sync channels not hate life */
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
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OUT_RING (evo, 0x00000311);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
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OUT_RING (evo, 0x00000311);
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FIRE_RING(evo);
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if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
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NV_ERROR(dev, "evo pushbuf stalled\n");
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@ -366,6 +371,122 @@ nv50_display_destroy(struct drm_device *dev)
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kfree(disp);
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}
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void
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nv50_display_flip_stop(struct drm_crtc *crtc)
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{
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struct nv50_display *disp = nv50_display(crtc->dev);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
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struct nouveau_channel *evo = dispc->sync;
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int ret;
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ret = RING_SPACE(evo, 8);
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if (ret) {
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WARN_ON(1);
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return;
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}
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BEGIN_RING(evo, 0, 0x0084, 1);
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OUT_RING (evo, 0x00000000);
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BEGIN_RING(evo, 0, 0x0094, 1);
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OUT_RING (evo, 0x00000000);
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BEGIN_RING(evo, 0, 0x00c0, 1);
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OUT_RING (evo, 0x00000000);
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BEGIN_RING(evo, 0, 0x0080, 1);
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OUT_RING (evo, 0x00000000);
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FIRE_RING (evo);
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}
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int
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nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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struct nouveau_channel *chan)
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{
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struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
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struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
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struct nv50_display *disp = nv50_display(crtc->dev);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
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struct nouveau_channel *evo = dispc->sync;
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int ret;
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ret = RING_SPACE(evo, 24);
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if (unlikely(ret))
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return ret;
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/* synchronise with the rendering channel, if necessary */
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if (likely(chan)) {
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u64 offset = dispc->sem.bo->vma.offset + dispc->sem.offset;
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ret = RING_SPACE(chan, 10);
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if (ret) {
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WIND_RING(evo);
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return ret;
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}
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if (dev_priv->chipset < 0xc0) {
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BEGIN_RING(chan, NvSubSw, 0x0060, 2);
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OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
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OUT_RING (chan, dispc->sem.offset);
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BEGIN_RING(chan, NvSubSw, 0x006c, 1);
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OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
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BEGIN_RING(chan, NvSubSw, 0x0064, 2);
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OUT_RING (chan, dispc->sem.offset ^ 0x10);
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OUT_RING (chan, 0x74b1e000);
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BEGIN_RING(chan, NvSubSw, 0x0060, 1);
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if (dev_priv->chipset < 0x84)
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OUT_RING (chan, NvSema);
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else
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OUT_RING (chan, chan->vram_handle);
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} else {
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BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset));
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OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
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OUT_RING (chan, 0x1002);
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BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset ^ 0x10));
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OUT_RING (chan, 0x74b1e000);
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OUT_RING (chan, 0x1001);
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}
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FIRE_RING (chan);
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} else {
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nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
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0xf00d0000 | dispc->sem.value);
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}
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/* queue the flip on the crtc's "display sync" channel */
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BEGIN_RING(evo, 0, 0x0100, 1);
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OUT_RING (evo, 0xfffe0000);
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BEGIN_RING(evo, 0, 0x0084, 5);
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OUT_RING (evo, chan ? 0x00000100 : 0x00000010);
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OUT_RING (evo, dispc->sem.offset);
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OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
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OUT_RING (evo, 0x74b1e000);
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OUT_RING (evo, NvEvoSync);
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BEGIN_RING(evo, 0, 0x00a0, 2);
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OUT_RING (evo, 0x00000000);
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OUT_RING (evo, 0x00000000);
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BEGIN_RING(evo, 0, 0x00c0, 1);
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OUT_RING (evo, nv_fb->r_dma);
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BEGIN_RING(evo, 0, 0x0110, 2);
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OUT_RING (evo, 0x00000000);
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OUT_RING (evo, 0x00000000);
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BEGIN_RING(evo, 0, 0x0800, 5);
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OUT_RING (evo, (nv_fb->nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
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OUT_RING (evo, 0);
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OUT_RING (evo, (fb->height << 16) | fb->width);
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OUT_RING (evo, nv_fb->r_pitch);
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OUT_RING (evo, nv_fb->r_format);
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BEGIN_RING(evo, 0, 0x0080, 1);
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OUT_RING (evo, 0x00000000);
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FIRE_RING (evo);
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dispc->sem.offset ^= 0x10;
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dispc->sem.value++;
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return 0;
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}
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static u16
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nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
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u32 mc, int pxclk)
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@ -35,10 +35,21 @@
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#include "nouveau_crtc.h"
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#include "nv50_evo.h"
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struct nv50_display_crtc {
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struct nouveau_channel *sync;
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struct {
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struct nouveau_bo *bo;
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u32 offset;
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u16 value;
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} sem;
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};
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struct nv50_display {
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struct nouveau_channel *master;
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struct nouveau_gpuobj *ntfy;
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struct nv50_display_crtc crtc[2];
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struct tasklet_struct tasklet;
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struct {
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struct dcb_entry *dcb;
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@ -62,6 +73,10 @@ void nv50_display_destroy(struct drm_device *dev);
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int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
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int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
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int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
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struct nouveau_channel *chan);
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void nv50_display_flip_stop(struct drm_crtc *);
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int nv50_evo_init(struct drm_device *dev);
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void nv50_evo_fini(struct drm_device *dev);
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void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
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@ -220,7 +220,15 @@ static void
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nv50_evo_destroy(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sem.bo) {
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nouveau_bo_unmap(disp->crtc[i].sem.bo);
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nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
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}
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nv50_evo_channel_del(&disp->crtc[i].sync);
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}
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nouveau_gpuobj_ref(NULL, &disp->ntfy);
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nv50_evo_channel_del(&disp->master);
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}
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@ -232,7 +240,7 @@ nv50_evo_create(struct drm_device *dev)
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struct nv50_display *disp = nv50_display(dev);
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struct nouveau_gpuobj *ramht = NULL;
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struct nouveau_channel *evo;
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int ret;
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int ret, i, j;
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/* create primary evo channel, the one we use for modesetting
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* purporses
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@ -311,6 +319,61 @@ nv50_evo_create(struct drm_device *dev)
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if (ret)
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goto err;
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/* create "display sync" channels and other structures we need
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* to implement page flipping
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*/
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for (i = 0; i < 2; i++) {
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struct nv50_display_crtc *dispc = &disp->crtc[i];
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u64 offset;
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ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
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if (ret)
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goto err;
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ret = nouveau_bo_new(dev, NULL, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, false, true, &dispc->sem.bo);
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if (!ret) {
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offset = dispc->sem.bo->bo.mem.start << PAGE_SHIFT;
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ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(dispc->sem.bo);
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if (ret)
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nouveau_bo_ref(NULL, &dispc->sem.bo);
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}
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
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offset, 4096, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
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(dev_priv->chipset < 0xc0 ?
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0x7a00 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
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(dev_priv->chipset < 0xc0 ?
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0x7000 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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for (j = 0; j < 4096; j += 4)
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nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
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dispc->sem.offset = 0;
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}
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return 0;
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err:
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@ -322,7 +385,7 @@ int
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nv50_evo_init(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int ret;
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int ret, i;
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if (!disp->master) {
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ret = nv50_evo_create(dev);
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@ -330,15 +393,32 @@ nv50_evo_init(struct drm_device *dev)
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return ret;
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}
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return nv50_evo_channel_init(disp->master);
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ret = nv50_evo_channel_init(disp->master);
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if (ret)
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return ret;
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for (i = 0; i < 2; i++) {
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ret = nv50_evo_channel_init(disp->crtc[i].sync);
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if (ret)
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return ret;
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}
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return 0;
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}
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void
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nv50_evo_fini(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sync)
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nv50_evo_channel_fini(disp->crtc[i].sync);
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}
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if (disp->master)
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nv50_evo_channel_fini(disp->master);
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nv50_evo_destroy(dev);
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}
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@ -113,5 +113,7 @@
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/* Both of these are needed, otherwise nothing happens. */
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#define NV50_EVO_CRTC_SCALE_RES1 0x000008d8
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#define NV50_EVO_CRTC_SCALE_RES2 0x000008dc
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#define NV50_EVO_CRTC_UNK900 0x00000900
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#define NV50_EVO_CRTC_UNK904 0x00000904
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#endif
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