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dt-bindings: Changes for v5.16-rc1
This contains the DT bindings for the NVDEC hardware video decoder found on Tegra210 and later chips as well as a node name fix for the examples in the Tegra194 PCIe controller (endpoint mode) DT bindings. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmFgnvwTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoeCFD/9cJsKiAMicIQurlDVI02Dxf6VKHbxX 11z1jPWzOwBkLrvDISjpWkgN8CMuPEg2NHlZ2ei87nqqFPKWsvPVsib3iHUAy8QY EVgI5Y56VFamH8mBmiPlSe0XB3vcdIx+3xivylDiHRRYwX/VaVl5hGi5BZM903Iv T2/Ompq7Jyeif4yH+GOIbwS4gGVQKi+LywpYAMac1NfYWP4DrBCqLh5VyNZD5t2T 9OgDby8DrhnAtGpTOyrrQfsPo42+N1LDufP3iU7Bx28fdQWRCcth130ZABNKtOR0 4e0V21lnHlyMWZyjABuXxEX2cPy/MlSa3X9RCZsH7FJdYSZdQFzBvRnGC58PERek I2x0JIuYmQh/3LvbRMKVKdkd3qWdKEWaaHES/i/A+gBbQloHYEIp3fkkga8SmU21 BwCMB/OtPbpRI62aXSQ6C0VHLKdqwdHHwkjpbvdo2tQQfO5MdW074hLMAQacmzIj B7qg55bt465lL6253oCjXswN/CBlHqQ7OJNUE0EIbKsRGy4u3L9YdKPZwidn+qB2 xArO0CkybZO3shPnwvzeZ2bZ34oU3tPgAYZI8UrGDgUB/lgjKVQeDGwQb0gbKCkS w3L+xnS7L2XbjHwXL73x0YVtUWYFVl7zvLcgDf73slOydO+2P34x6nylsNmhD19p lZAKTDbxlsX8XA== =TONa -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmFklpwACgkQmmx57+YA GNnsoBAAgWmtn9EZOA4QVWwgcGoBU9BE8iEiJQe7ENupZ+ofjQvez6p57AM0phfM b2sctz66Rba2SabBqq8fGt1zOMH3RAmnY8QNhdJX22xyLltmX7dPJV2VlTBVTOGn p69aVgUL1cLIU7LGdUAW5fTgiu5kNLG+XsFZaIPh0iVy9tDfwFs1hYNWnasivm2u 1A/sp+NGVA/YNdvun6gU/hXOqG20YFAUxushZthDZwdspYnyB5JBkNyRC27LQknb cJ9Y/su3PWKNZrE6e0Kcln7mhZ4303vciZfhzVrrG3HpKxu2jrowNKTbZLhJFXRp JkCY/bhhPc9VpZPfc34tBdiU7Y7Xo44R3IdqY77/+Pi0wXpxFyY+b0rAFSqWlOag j489y4Casg7wPebpvmhi+YtkmujpxLV455V/qb8Nyu8Zv5TNAjkb/sGDXnRsSrZl ijNXJ40/DknbAXeXFLbhWzuuKxN6wAKGgZTPAsPVchgTDll7IULJERZlgXzc4KKg rN0f7r00ECj0uS6Wm66+HUtPvQrTJE8w8++dhFzUXeR8mjUTUbD2TJ7XaFHlDAzQ qUpa8UylfJvUsHvQIPQKUnNEc0jQrkAkgI5YCRa+5szIKIx/KtDCyD6AVJgGo+0c QvK0xsU5h/U+KUjtuJG5uzOSH08U57T1F1JZVdoB/CG6lEIPkL8= =cvhE -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.16-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.16-rc1 This contains the DT bindings for the NVDEC hardware video decoder found on Tegra210 and later chips as well as a node name fix for the examples in the Tegra194 PCIe controller (endpoint mode) DT bindings. * tag 'tegra-for-5.16-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: PCI: tegra194: Fix PCIe endpoint node names dt-bindings: Add YAML bindings for NVDEC Link: https://lore.kernel.org/r/20211008201132.1678814-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Device tree binding for NVIDIA Tegra NVDEC
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description: |
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NVDEC is the hardware video decoder present on NVIDIA Tegra210
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and newer chips. It is located on the Host1x bus and typically
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programmed through Host1x channels.
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maintainers:
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- Thierry Reding <treding@gmail.com>
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- Mikko Perttunen <mperttunen@nvidia.com>
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properties:
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$nodename:
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pattern: "^nvdec@[0-9a-f]*$"
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compatible:
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enum:
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- nvidia,tegra210-nvdec
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- nvidia,tegra186-nvdec
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- nvidia,tegra194-nvdec
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: nvdec
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: nvdec
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 1
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dma-coherent: true
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interconnects:
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items:
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- description: DMA read memory client
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- description: DMA read 2 memory client
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- description: DMA write memory client
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interconnect-names:
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items:
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- const: dma-mem
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- const: read-1
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- const: write
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nvidia,host1x-class:
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description: |
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Host1x class of the engine, used to specify the targeted engine
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when programming the engine through Host1x channels or when
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configuring engine-specific behavior in Host1x.
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default: 0xf0
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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nvdec@15480000 {
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compatible = "nvidia,tegra186-nvdec";
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reg = <0x15480000 0x40000>;
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clocks = <&bpmp TEGRA186_CLK_NVDEC>;
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clock-names = "nvdec";
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resets = <&bpmp TEGRA186_RESET_NVDEC>;
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reset-names = "nvdec";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
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interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
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interconnect-names = "dma-mem", "read-1", "write";
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iommus = <&smmu TEGRA186_SID_NVDEC>;
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};
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@ -197,7 +197,7 @@ Tegra194 RC mode:
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Tegra194 EP mode:
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Tegra194 EP mode:
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-----------------
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-----------------
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pcie_ep@141a0000 {
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pcie-ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
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compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
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reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
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@ -6285,6 +6285,7 @@ L: linux-tegra@vger.kernel.org
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S: Supported
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S: Supported
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T: git git://anongit.freedesktop.org/tegra/linux.git
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T: git git://anongit.freedesktop.org/tegra/linux.git
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F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
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F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
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F: Documentation/devicetree/bindings/gpu/host1x/
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F: drivers/gpu/drm/tegra/
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F: drivers/gpu/drm/tegra/
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F: drivers/gpu/host1x/
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F: drivers/gpu/host1x/
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F: include/linux/host1x.h
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F: include/linux/host1x.h
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