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ARM: shmobile: emev2: add IIC cores to dtsi
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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parent
7bf46d0be2
commit
cd42d042a2
@ -21,6 +21,8 @@
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &iic0;
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i2c1 = &iic1;
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};
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cpus {
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@ -66,6 +68,30 @@
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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iic0_sclkdiv: iic0_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x624 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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iic0_sclk: iic0_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x48c 1>;
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clocks = <&iic0_sclkdiv>;
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#clock-cells = <0>;
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};
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iic1_sclkdiv: iic1_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x624 16>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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iic1_sclk: iic1_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x490 1>;
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clocks = <&iic1_sclkdiv>;
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#clock-cells = <0>;
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};
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pll3_fo: pll3_fo {
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compatible = "fixed-factor-clock";
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clocks = <&c32ki>;
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@ -234,4 +260,26 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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iic0: i2c@e0070000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-emev2";
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reg = <0xe0070000 0x28>;
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interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
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clocks = <&iic0_sclk>;
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clock-names = "sclk";
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status = "disabled";
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};
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iic1: i2c@e10a0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-emev2";
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reg = <0xe10a0000 0x28>;
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interrupts = <0 33 IRQ_TYPE_EDGE_RISING>;
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clocks = <&iic1_sclk>;
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clock-names = "sclk";
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status = "disabled";
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};
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};
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