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perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs

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perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with
the same value. Add a little optimization to skip the unnecessary
write.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Andi Kleen 2015-03-20 10:11:24 -07:00 committed by Ingo Molnar
parent 1a78d93750
commit cd1f11de69
1 changed files with 4 additions and 2 deletions
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6
arch/x86/kernel/cpu/perf_event_intel_lbr.c
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@ -135,7 +135,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
static void __intel_pmu_lbr_enable(bool pmi)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
u64 debugctl, lbr_select = 0;
u64 debugctl, lbr_select = 0, orig_debugctl;
/*
* No need to reprogram LBR_SELECT in a PMI, as it
@ -147,6 +147,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
}
rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
orig_debugctl = debugctl;
debugctl |= DEBUGCTLMSR_LBR;
/*
* LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
@ -155,7 +156,8 @@ static void __intel_pmu_lbr_enable(bool pmi)
*/
if (!(lbr_select & LBR_CALL_STACK))
debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
if (orig_debugctl != debugctl)
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
}
static void __intel_pmu_lbr_disable(void)