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media: camss: vfe: Configure scaler module in VFE

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Add scaler module configuration support to be able to apply scaling.

Signed-off-by: Todor Tomov <todor.tomov@linaro.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Todor Tomov 2017-08-08 09:30:13 -04:00 committed by Mauro Carvalho Chehab
parent 810b659880
commit cce91b1469
1 changed files with 46 additions and 13 deletions
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59
drivers/media/platform/qcom/camss-8x16/camss-vfe.c
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@ -198,13 +198,16 @@
#define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca
#define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9
#define VFE_0_SCALE_ENC_Y_CFG 0x75c
#define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760
#define VFE_0_SCALE_ENC_Y_H_PHASE 0x764
#define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c
#define VFE_0_SCALE_ENC_Y_V_PHASE 0x770
#define VFE_0_SCALE_ENC_CBCR_CFG 0x778 #define VFE_0_SCALE_ENC_CBCR_CFG 0x778
#define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c
#define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780
#define VFE_0_SCALE_ENC_CBCR_H_PAD 0x78c
#define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790
#define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794
#define VFE_0_SCALE_ENC_CBCR_V_PAD 0x7a0
#define VFE_0_CLAMP_ENC_MAX_CFG 0x874 #define VFE_0_CLAMP_ENC_MAX_CFG 0x874
#define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0)
@ -670,6 +673,20 @@ static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line)
writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);
} }
static inline u8 vfe_calc_interp_reso(u16 input, u16 output)
{
if (input / output >= 16)
return 0;
if (input / output >= 8)
return 1;
if (input / output >= 4)
return 2;
return 3;
}
static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line)
{ {
u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat;
@ -678,35 +695,51 @@ static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line)
u8 interp_reso; u8 interp_reso;
u32 phase_mult; u32 phase_mult;
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);
input = line->fmt[MSM_VFE_PAD_SINK].width;
output = line->compose.width;
reg = (output << 16) | input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);
interp_reso = vfe_calc_interp_reso(input, output);
phase_mult = input * (1 << (13 + interp_reso)) / output;
reg = (interp_reso << 20) | phase_mult;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);
input = line->fmt[MSM_VFE_PAD_SINK].height;
output = line->compose.height;
reg = (output << 16) | input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);
interp_reso = vfe_calc_interp_reso(input, output);
phase_mult = input * (1 << (13 + interp_reso)) / output;
reg = (interp_reso << 20) | phase_mult;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);
writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);
input = line->fmt[MSM_VFE_PAD_SINK].width; input = line->fmt[MSM_VFE_PAD_SINK].width;
output = line->fmt[MSM_VFE_PAD_SRC].width / 2; output = line->compose.width / 2;
reg = (output << 16) | input; reg = (output << 16) | input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);
interp_reso = 3; interp_reso = vfe_calc_interp_reso(input, output);
phase_mult = input * (1 << (13 + interp_reso)) / output; phase_mult = input * (1 << (13 + interp_reso)) / output;
reg = (interp_reso << 20) | phase_mult; reg = (interp_reso << 20) | phase_mult;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);
reg = input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PAD);
input = line->fmt[MSM_VFE_PAD_SINK].height; input = line->fmt[MSM_VFE_PAD_SINK].height;
output = line->fmt[MSM_VFE_PAD_SRC].height; output = line->compose.height;
if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21)
output = line->fmt[MSM_VFE_PAD_SRC].height / 2; output = line->compose.height / 2;
reg = (output << 16) | input; reg = (output << 16) | input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);
interp_reso = 3; interp_reso = vfe_calc_interp_reso(input, output);
phase_mult = input * (1 << (13 + interp_reso)) / output; phase_mult = input * (1 << (13 + interp_reso)) / output;
reg = (interp_reso << 20) | phase_mult; reg = (interp_reso << 20) | phase_mult;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);
reg = input;
writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PAD);
} }
static void vfe_set_clamp_cfg(struct vfe_device *vfe) static void vfe_set_clamp_cfg(struct vfe_device *vfe)