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ALSA: ad1889: Fix probable mask then right shift defects
Precedence of & and >> is not the same and is not left to right. shift has higher precedence and should be done after the mask. Add parentheses around the mask. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -681,7 +681,7 @@ snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffe
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/* WARQ is at offset 12 */
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tmp = (reg & AD_DS_WSMC_WARQ) ?
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(((reg & AD_DS_WSMC_WARQ >> 12) & 0x01) ? 12 : 18) : 4;
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((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4;
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tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
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snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
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@ -693,7 +693,7 @@ snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffe
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/* SYRQ is at offset 4 */
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tmp = (reg & AD_DS_WSMC_SYRQ) ?
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(((reg & AD_DS_WSMC_SYRQ >> 4) & 0x01) ? 12 : 18) : 4;
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((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4;
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tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
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snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
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@ -709,7 +709,7 @@ snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffe
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/* ACRQ is at offset 4 */
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tmp = (reg & AD_DS_RAMC_ACRQ) ?
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(((reg & AD_DS_RAMC_ACRQ >> 4) & 0x01) ? 12 : 18) : 4;
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((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4;
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tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
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snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
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@ -720,7 +720,7 @@ snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffe
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/* RERQ is at offset 12 */
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tmp = (reg & AD_DS_RAMC_RERQ) ?
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(((reg & AD_DS_RAMC_RERQ >> 12) & 0x01) ? 12 : 18) : 4;
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((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4;
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tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
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snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
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