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ARM: dts: i.MX6: Add BTicino i.MX6DL Mamoj initial support
This patch adds initial support for BTicino i.MX6DL Mamoj board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Simone CIANNI <simone.cianni@bticino.it> Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Jagan Teki
Shawn Guo
parent
83dcec32f2
commit
cc2475445e
@ -399,6 +399,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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imx6dl-hummingboard2-som-v15.dtb \
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imx6dl-icore.dtb \
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imx6dl-icore-rqs.dtb \
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imx6dl-mamoj.dtb \
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imx6dl-nit6xlite.dtb \
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imx6dl-nitrogen6x.dtb \
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imx6dl-phytec-mira-rdk-nand.dtb \
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224
arch/arm/boot/dts/imx6dl-mamoj.dts
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224
arch/arm/boot/dts/imx6dl-mamoj.dts
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@ -0,0 +1,224 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 BTicino
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* Copyright (C) 2018 Amarula Solutions B.V.
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*/
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/dts-v1/;
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#include "imx6dl.dtsi"
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/ {
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model = "BTicino i.MX6DL Mamoj board";
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compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "mii";
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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pfuze100: pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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/* CPU vdd_arm core */
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* SOC vdd_soc */
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* I/O power GEN_3V3 */
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* DDR memory */
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* DDR memory */
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sw3b_reg: sw3b {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* not used */
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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};
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/* not used */
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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/* PMIC vsnvs. EX boot mode */
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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/* not used */
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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/* not used */
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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/* not used */
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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/* 1v8 general power */
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* 2v8 general power IMX6 */
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* 3v3 Ethernet */
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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bus-width = <8>;
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non-removable;
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keep-power-in-suspend;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b1
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
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MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
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MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b1
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
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MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
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MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
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MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
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MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
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MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
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MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
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MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
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>;
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};
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};
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