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clk: tegra: add fence_delay for clock registers

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To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver 2018-01-25 16:00:11 +02:00 committed by Thierry Reding
parent 89e423c3f1
commit cbfc8d0a85
1 changed files with 7 additions and 0 deletions
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7
drivers/clk/tegra/clk.h
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@ -812,4 +812,11 @@ int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
/* Combined read fence with delay */
#define fence_udelay(delay, reg) \
do { \
readl(reg); \
udelay(delay); \
} while (0)
#endif /* TEGRA_CLK_H */