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drm/radeon/dce4+: optimize pageflip (v2)
Taking the grph update lock is only necessary when updating the the secondary address (for single pipe stereo). v2: fix comment as per Michel's suggestion Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1404,44 +1404,20 @@ void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
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* @crtc_id: crtc to cleanup pageflip on
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* @crtc_base: new address of the crtc (GPU MC address)
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*
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* Does the actual pageflip (evergreen+).
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* During vblank we take the crtc lock and wait for the update_pending
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* bit to go high, when it does, we release the lock, and allow the
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* double buffered update to take place.
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* Returns the current update pending status.
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* Triggers the actual pageflip by updating the primary
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* surface base address (evergreen+).
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*/
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void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
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{
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struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
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u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
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int i;
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/* Lock the graphics update lock */
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tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
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WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
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/* update the scanout addresses */
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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(u32)crtc_base);
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
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upper_32_bits(crtc_base));
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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(u32)crtc_base);
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/* Wait for update_pending to go high. */
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
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break;
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udelay(1);
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}
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DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
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/* Unlock the lock, so double-buffering can take place inside vblank */
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tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
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WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
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/* post the write */
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RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);
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}
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/**
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