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arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation

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This converts TRBBASER_EL1 register to automatic generation without
causing any functional change.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-11-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Anshuman Khandual 2023-06-14 12:29:45 +05:30 committed by Catalin Marinas
parent 6669697733
commit cbaf0cf005
2 changed files with 5 additions and 3 deletions
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3
arch/arm64/include/asm/sysreg.h
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@ -227,14 +227,11 @@
/*** End of Statistical Profiling Extension ***/ /*** End of Statistical Profiling Extension ***/
#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
#define TRBBASER_EL1_BASE_MASK GENMASK_ULL(63, 12)
#define TRBBASER_EL1_BASE_SHIFT 12
#define TRBSR_EL1_EC_MASK GENMASK(31, 26) #define TRBSR_EL1_EC_MASK GENMASK(31, 26)
#define TRBSR_EL1_EC_SHIFT 26 #define TRBSR_EL1_EC_SHIFT 26
#define TRBSR_EL1_IRQ BIT(22) #define TRBSR_EL1_IRQ BIT(22)

5
arch/arm64/tools/sysreg
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@ -2277,3 +2277,8 @@ EndSysreg
Sysreg TRBPTR_EL1 3 0 9 11 1 Sysreg TRBPTR_EL1 3 0 9 11 1
Field 63:0 PTR Field 63:0 PTR
EndSysreg EndSysreg
Sysreg TRBBASER_EL1 3 0 9 11 2
Field 63:12 BASE
Res0 11:0
EndSysreg