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ARM: 7927/1: dcache: select DCACHE_WORD_ACCESS for big-endian CPUs
With commit 11ec50caed
("word-at-a-time: provide generic big-endian
zero_bytemask implementation"), the asm-generic word-at-a-time code now
provides a zero_bytemask implementation, allowing us to make use of
DCACHE_WORD_ACCESS on big-endian CPUs, providing our
load_unaligned_zeropad function is endianness-clean.
This patch reworks the load_unaligned_zeropad fixup code to work for
both big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check
when selecting DCACHE_WORD_ACCESS.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
5d49750933
commit
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@ -12,7 +12,7 @@ config ARM
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select BUILDTIME_EXTABLE_SORT if MMU
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select CLONE_BACKWARDS
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select CPU_PM if (SUSPEND || CPU_IDLE)
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select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
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select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
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select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
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select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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select GENERIC_IDLE_POLL_SETUP
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@ -48,10 +48,14 @@ static inline unsigned long find_zero(unsigned long mask)
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return ret;
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}
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#ifdef CONFIG_DCACHE_WORD_ACCESS
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#define zero_bytemask(mask) (mask)
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#else /* __ARMEB__ */
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#include <asm-generic/word-at-a-time.h>
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#endif
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#ifdef CONFIG_DCACHE_WORD_ACCESS
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/*
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* Load an unaligned word from kernel space.
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*
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@ -73,7 +77,11 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
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" bic %2, %2, #0x3\n"
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" ldr %0, [%2]\n"
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" lsl %1, %1, #0x3\n"
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#ifndef __ARMEB__
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" lsr %0, %0, %1\n"
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#else
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" lsl %0, %0, %1\n"
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#endif
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" b 2b\n"
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" .popsection\n"
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" .pushsection __ex_table,\"a\"\n"
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@ -86,11 +94,5 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)
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return ret;
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}
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#endif /* DCACHE_WORD_ACCESS */
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#else /* __ARMEB__ */
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#include <asm-generic/word-at-a-time.h>
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#endif
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#endif /* __ASM_ARM_WORD_AT_A_TIME_H */
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