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ARM: dts: sun7i: fix device node ordering
This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -1542,6 +1542,22 @@
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status = "disabled";
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};
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ps20: ps2@01c2a000 {
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compatible = "allwinner,sun4i-a10-ps2";
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reg = <0x01c2a000 0x400>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 6>;
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status = "disabled";
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};
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ps21: ps2@01c2a400 {
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compatible = "allwinner,sun4i-a10-ps2";
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reg = <0x01c2a400 0x400>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 7>;
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status = "disabled";
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};
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun7i-a20-i2c",
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"allwinner,sun4i-a10-i2c";
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@ -1642,20 +1658,5 @@
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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ps20: ps2@01c2a000 {
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compatible = "allwinner,sun4i-a10-ps2";
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reg = <0x01c2a000 0x400>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 6>;
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status = "disabled";
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};
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ps21: ps2@01c2a400 {
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compatible = "allwinner,sun4i-a10-ps2";
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reg = <0x01c2a400 0x400>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 7>;
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status = "disabled";
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};
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};
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};
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