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ARM: OMAP4: clock: Add 44xx data using common struct clk

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This patch is output from updated omap hw data autogeneration scripts
mostly contributed by Mike Turquette, with some later fixes from me.
All data is added into a new cclock44xx_data.c file which will be
switched with clock44xx_data.c file in a later patch.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: replace omap2_init_clksel_parent() with
 omap2_clksel_find_parent_index(); reflowed macros; updated
 DEFINE_STRUCT_CLK_HW_OMAP macro to include clkdm_name;
 use macros for clksel mux+gate clocks; many other fixes]
[mturquette@ti.com: converted DPLL outputs to HSDIVIDER macro; trace_clk_div_ck
 has clkdm ops]
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: fixed the omap-gpmc.fck alias per commit a2e5b90b; fixed
 several checkpatch issues; moved the dpll3xxx.c clockdomain modifications to
 another patch]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Rajendra Nayak 2012-11-06 15:41:08 -07:00 committed by Paul Walmsley
parent 8c725dcd22
commit cb26867ee2
5 changed files with 2013 additions and 8 deletions
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1987
arch/arm/mach-omap2/cclock44xx_data.c Normal file
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File diff suppressed because it is too large Load Diff

2
arch/arm/mach-omap2/clock.h
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@ -641,6 +641,7 @@ extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
#ifdef CONFIG_COMMON_CLK
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
@ -673,6 +674,7 @@ extern const struct clkops clkops_omap4_dpllmx_ops;
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
extern const struct clksel_rate div_1_0_rates[];
extern const struct clksel_rate div3_1to4_rates[];
extern const struct clksel_rate div_1_1_rates[];
extern const struct clksel_rate div_1_2_rates[];
extern const struct clksel_rate div_1_3_rates[];

8
arch/arm/mach-omap2/clock44xx_data.c
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@ -275,13 +275,6 @@ static struct clk abe_24m_fclk = {
.recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel_rate div3_1to4_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 4, .val = 2, .flags = RATE_IN_4430 },
{ .div = 0 },
};
static const struct clksel abe_clk_div[] = {
{ .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
@ -677,7 +670,6 @@ static struct dpll_data dpll_mpu_dd = {
.min_divider = 1,
};
static struct clk dpll_mpu_ck = {
.name = "dpll_mpu_ck",
.parent = &sys_clkin_ck,

22
arch/arm/mach-omap2/clock_common_data.c
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@ -52,6 +52,13 @@ const struct clksel_rate div_1_0_rates[] = {
{ .div = 0 },
};
const struct clksel_rate div3_1to4_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 4, .val = 2, .flags = RATE_IN_4430 },
{ .div = 0 },
};
const struct clksel_rate div_1_1_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
{ .div = 0 },
@ -108,6 +115,19 @@ const struct clksel_rate div31_1to31_rates[] = {
};
/* Clocks shared between various OMAP SoCs */
#ifdef CONFIG_COMMON_CLK
#include <linux/clk-private.h>
static struct clk_ops dummy_ck_ops = {};
struct clk dummy_ck = {
.name = "dummy_clk",
.ops = &dummy_ck_ops,
.flags = CLK_IS_BASIC,
};
#else
struct clk virt_19200000_ck = {
.name = "virt_19200000_ck",
@ -120,3 +140,5 @@ struct clk virt_26000000_ck = {
.ops = &clkops_null,
.rate = 26000000,
};
#endif

2
arch/arm/mach-omap2/scrm44xx.h
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@ -127,12 +127,14 @@
/* AUXCLKREQ0 */
#define OMAP4_MAPPING_SHIFT 2
#define OMAP4_MAPPING_MASK (0x7 << 2)
#define OMAP4_MAPPING_WIDTH 3
#define OMAP4_ACCURACY_SHIFT 1
#define OMAP4_ACCURACY_MASK (1 << 1)
/* AUXCLK0 */
#define OMAP4_CLKDIV_SHIFT 16
#define OMAP4_CLKDIV_MASK (0xf << 16)
#define OMAP4_CLKDIV_WIDTH 4
#define OMAP4_DISABLECLK_SHIFT 9
#define OMAP4_DISABLECLK_MASK (1 << 9)
#define OMAP4_ENABLE_SHIFT 8