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KVM: x86: Refactor the MMIO SPTE generation handling
The code to propagate the memslots generation number into MMIO sptes is a bit convoluted. The "what" is relatively straightfoward, e.g. the comment explaining which bits go where is quite readable, but the "how" requires a lot of staring to understand what is happening. For example, 'MMIO_GEN_LOW_SHIFT' is actually used to calculate the high bits of the spte, while 'MMIO_SPTE_GEN_LOW_SHIFT' is used to calculate the low bits. Refactor the code to: - use #defines whose values align with the bits defined in the comment - use consistent code for both the high and low mask - explicitly highlight the handling of bit 0 (update in-progress flag) - explicitly call out that the defines are for MMIO sptes (to avoid confusion with the per-vCPU MMIO cache, which uses the full memslots generation) In addition to making the code a little less magical, this paves the way for moving the update in-progress flag to bit 63 without having to simultaneously rewrite all of the MMIO spte code. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -332,30 +332,41 @@ static inline bool is_access_track_spte(u64 spte)
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}
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/*
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* the low bit of the generation number is always presumed to be zero.
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* This disables mmio caching during memslot updates. The concept is
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* similar to a seqcount but instead of retrying the access we just punt
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* and ignore the cache.
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* Due to limited space in PTEs, the MMIO generation is a 19 bit subset of
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* the memslots generation and is derived as follows:
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*
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* spte bits 3-11 are used as bits 1-9 of the generation number,
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* the bits 52-61 are used as bits 10-19 of the generation number.
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* Bits 1-9 of the memslot generation are propagated to spte bits 3-11
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* Bits 10-19 of the memslot generation are propagated to spte bits 52-61
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*
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* The MMIO generation starts at bit 1 of the memslots generation in order to
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* skip over bit 0, the KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag. Including
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* the flag would require stealing a bit from the "real" generation number and
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* thus effectively halve the maximum number of MMIO generations that can be
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* handled before encountering a wrap (which requires a full MMU zap). The
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* flag is instead explicitly queried when checking for MMIO spte cache hits.
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*/
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#define MMIO_SPTE_GEN_LOW_SHIFT 2
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#define MMIO_SPTE_GEN_HIGH_SHIFT 52
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#define MMIO_SPTE_GEN_MASK GENMASK_ULL(19, 1)
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#define MMIO_SPTE_GEN_SHIFT 1
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#define MMIO_GEN_SHIFT 20
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#define MMIO_GEN_LOW_SHIFT 10
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#define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
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#define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
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#define MMIO_SPTE_GEN_LOW_START 3
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#define MMIO_SPTE_GEN_LOW_END 11
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#define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
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MMIO_SPTE_GEN_LOW_START)
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#define MMIO_SPTE_GEN_HIGH_START 52
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#define MMIO_SPTE_GEN_HIGH_END 61
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#define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
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MMIO_SPTE_GEN_HIGH_START)
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static u64 generation_mmio_spte_mask(u64 gen)
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{
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u64 mask;
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WARN_ON(gen & ~MMIO_GEN_MASK);
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WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
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mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
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mask |= (gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
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gen >>= MMIO_SPTE_GEN_SHIFT;
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mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK;
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mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK;
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return mask;
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}
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@ -365,20 +376,15 @@ static u64 get_mmio_spte_generation(u64 spte)
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spte &= ~shadow_mmio_mask;
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gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
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gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
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return gen;
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}
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static u64 kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
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gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START;
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gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START;
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return gen << MMIO_SPTE_GEN_SHIFT;
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}
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static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
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unsigned access)
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{
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u64 gen = kvm_current_mmio_generation(vcpu);
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u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
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u64 mask = generation_mmio_spte_mask(gen);
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u64 gpa = gfn << PAGE_SHIFT;
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@ -409,7 +415,7 @@ static gfn_t get_mmio_spte_gfn(u64 spte)
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static unsigned get_mmio_spte_access(u64 spte)
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{
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u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
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u64 mask = generation_mmio_spte_mask(MMIO_SPTE_GEN_MASK) | shadow_mmio_mask;
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return (spte & ~mask) & ~PAGE_MASK;
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}
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@ -426,9 +432,13 @@ static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
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static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
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{
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u64 kvm_gen, spte_gen;
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u64 kvm_gen, spte_gen, gen;
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kvm_gen = kvm_current_mmio_generation(vcpu);
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gen = kvm_vcpu_memslots(vcpu)->generation;
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if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
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return false;
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kvm_gen = gen & MMIO_SPTE_GEN_MASK;
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spte_gen = get_mmio_spte_generation(spte);
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trace_check_mmio_spte(spte, kvm_gen, spte_gen);
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@ -5895,13 +5905,13 @@ static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
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void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
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{
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gen &= MMIO_GEN_MASK;
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gen &= MMIO_SPTE_GEN_MASK;
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/*
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* Shift to eliminate the "update in-progress" flag, which isn't
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* included in the spte's generation number.
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* Shift to adjust for the "update in-progress" flag, which isn't
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* included in the MMIO generation number.
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*/
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gen >>= 1;
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gen >>= MMIO_SPTE_GEN_SHIFT;
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/*
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* Generation numbers are incremented in multiples of the number of
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