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drm/radeon/si: enable DMA pg by default
Enable DMA powergating by default. The DMA engines will be powergated when not in use. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2389,9 +2389,9 @@ int radeon_asic_init(struct radeon_device *rdev)
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RADEON_CG_SUPPORT_UVD_MGCG |
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RADEON_CG_SUPPORT_HDP_LS |
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RADEON_CG_SUPPORT_HDP_MGCG;
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rdev->pg_flags = 0;
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/*RADEON_PG_SUPPORT_GFX_CG |
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RADEON_PG_SUPPORT_SDMA;*/
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rdev->pg_flags = 0 |
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/*RADEON_PG_SUPPORT_GFX_CG | */
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RADEON_PG_SUPPORT_SDMA;
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break;
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case CHIP_OLAND:
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rdev->cg_flags =
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@ -5279,13 +5279,6 @@ static void si_fini_cg(struct radeon_device *rdev)
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RADEON_CG_BLOCK_HDP), false);
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}
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void si_update_pg(struct radeon_device *rdev,
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bool enable)
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{
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si_enable_dma_pg(rdev, enable);
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si_enable_gfx_cgpg(rdev, enable);
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}
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u32 si_get_csb_size(struct radeon_device *rdev)
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{
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u32 count = 0;
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@ -5387,7 +5380,8 @@ static void si_init_pg(struct radeon_device *rdev)
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
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si_init_gfx_cgpg(rdev);
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}
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si_update_pg(rdev, false);
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si_enable_dma_pg(rdev, true);
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si_enable_gfx_cgpg(rdev, true);
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} else {
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WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
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WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
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@ -5397,10 +5391,8 @@ static void si_init_pg(struct radeon_device *rdev)
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static void si_fini_pg(struct radeon_device *rdev)
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{
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if (rdev->pg_flags) {
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if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)
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si_enable_dma_pg(rdev, false);
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)
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si_enable_gfx_cgpg(rdev, false);
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si_enable_dma_pg(rdev, false);
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si_enable_gfx_cgpg(rdev, false);
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}
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}
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