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ARM: dts: exynos: Add soc node to exynos5440
The exynos5440 device tree is the only one left, which does not use "soc" node. Add a "soc" node to exynos5440.dtsi in order to make it consistent with other exynos DTS. Signed-off-by: Maciej Purski <m.purski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Maciej Purski
Krzysztof Kozlowski
parent
9097b4bd9f
commit
ca42d8d86c
@ -26,24 +26,6 @@
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tmuctrl2 = &tmuctrl_2;
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};
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clock: clock-controller@160000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@2e0000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2E1000 0x1000>,
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<0x2E2000 0x2000>,
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<0x2E4000 0x2000>,
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<0x2E6000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -70,182 +52,290 @@
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <50000000>;
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};
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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operating-points = <
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/* KHz uV */
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1500000 1100000
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1400000 1075000
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1300000 1050000
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1200000 1025000
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1100000 1000000
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1000000 975000
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900000 950000
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800000 925000
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>;
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};
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serial_0: serial@b0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial_1: serial@c0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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spi_0: spi@d0000 {
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compatible = "samsung,exynos5440-spi";
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reg = <0xD0000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,spi-src-clk = <0>;
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num-cs = <1>;
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clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
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clock-names = "spi", "spi_busclk0";
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};
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pin_ctrl: pinctrl@e0000 {
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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fan: fan {
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samsung,exynos5440-pin-function = <1>;
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};
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hdd_led0: hdd_led0 {
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samsung,exynos5440-pin-function = <2>;
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};
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hdd_led1: hdd_led1 {
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samsung,exynos5440-pin-function = <3>;
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};
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uart1: uart1 {
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samsung,exynos5440-pin-function = <4>;
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};
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};
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i2c@f0000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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i2c@100000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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watchdog@110000 {
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compatible = "samsung,s3c6410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "watchdog";
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};
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gmac: ethernet@230000 {
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compatible = "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0x00230000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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phy-mode = "sgmii";
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clocks = <&clock CLK_GMAC0>;
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clock-names = "stmmaceth";
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};
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amba {
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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};
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rtc@130000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "rtc";
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};
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clock: clock-controller@160000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x1000>;
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#clock-cells = <1>;
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};
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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gic: interrupt-controller@2e0000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2E1000 0x1000>,
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<0x2E2000 0x2000>,
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<0x2E4000 0x2000>,
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<0x2E6000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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tmuctrl_1: tmuctrl@16011c {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x16011C 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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tmuctrl_2: tmuctrl@160120 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160120 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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arm-pmu {
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compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <50000000>;
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};
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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operating-points = <
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/* KHz uV */
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1500000 1100000
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1400000 1075000
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1300000 1050000
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1200000 1025000
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1100000 1000000
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1000000 975000
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900000 950000
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800000 925000
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>;
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};
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serial_0: serial@b0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial_1: serial@c0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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spi_0: spi@d0000 {
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compatible = "samsung,exynos5440-spi";
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reg = <0xD0000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,spi-src-clk = <0>;
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num-cs = <1>;
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clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
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clock-names = "spi", "spi_busclk0";
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};
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pin_ctrl: pinctrl@e0000 {
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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fan: fan {
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samsung,exynos5440-pin-function = <1>;
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};
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hdd_led0: hdd_led0 {
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samsung,exynos5440-pin-function = <2>;
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};
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hdd_led1: hdd_led1 {
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samsung,exynos5440-pin-function = <3>;
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};
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uart1: uart1 {
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samsung,exynos5440-pin-function = <4>;
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};
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};
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i2c@f0000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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i2c@100000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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clock-names = "i2c";
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};
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watchdog@110000 {
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compatible = "samsung,s3c6410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "watchdog";
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};
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gmac: ethernet@230000 {
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compatible = "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0x00230000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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phy-mode = "sgmii";
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clocks = <&clock CLK_GMAC0>;
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clock-names = "stmmaceth";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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};
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rtc@130000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "rtc";
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};
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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tmuctrl_1: tmuctrl@16011c {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x16011C 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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tmuctrl_2: tmuctrl@160120 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160120 0x230>, <0x160368 0x10>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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};
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sata@210000 {
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compatible = "snps,exynos5440-ahci";
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reg = <0x210000 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SATA>;
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clock-names = "sata";
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};
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ohci@220000 {
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compatible = "samsung,exynos5440-ohci";
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reg = <0x220000 0x1000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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ehci@221000 {
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compatible = "samsung,exynos5440-ehci";
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reg = <0x221000 0x1000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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||||
pcie_phy0: pcie-phy@270000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x270000 0x1000>, <0x271000 0x40>;
|
||||
};
|
||||
|
||||
pcie_phy1: pcie-phy@272000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x272000 0x1000>, <0x271040 0x40>;
|
||||
};
|
||||
|
||||
pcie_0: pcie@290000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x290000 0x1000>, <0x40000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy0>;
|
||||
ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 53>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_1: pcie@2a0000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy1>;
|
||||
ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 56>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
@ -262,86 +352,4 @@
|
||||
#include "exynos5440-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
sata@210000 {
|
||||
compatible = "snps,exynos5440-ahci";
|
||||
reg = <0x210000 0x10000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_SATA>;
|
||||
clock-names = "sata";
|
||||
};
|
||||
|
||||
ohci@220000 {
|
||||
compatible = "samsung,exynos5440-ohci";
|
||||
reg = <0x220000 0x1000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
ehci@221000 {
|
||||
compatible = "samsung,exynos5440-ehci";
|
||||
reg = <0x221000 0x1000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_USB>;
|
||||
clock-names = "usbhost";
|
||||
};
|
||||
|
||||
pcie_phy0: pcie-phy@270000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x270000 0x1000>, <0x271000 0x40>;
|
||||
};
|
||||
|
||||
pcie_phy1: pcie-phy@272000 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "samsung,exynos5440-pcie-phy";
|
||||
reg = <0x272000 0x1000>, <0x271040 0x40>;
|
||||
};
|
||||
|
||||
pcie_0: pcie@290000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x290000 0x1000>, <0x40000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy0>;
|
||||
ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 53>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_1: pcie@2a0000 {
|
||||
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
|
||||
reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
|
||||
reg-names = "elbi", "config";
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
|
||||
clock-names = "pcie", "pcie_bus";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
phys = <&pcie_phy1>;
|
||||
ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
|
||||
bus-range = <0x00 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0x0 0 &gic 56>;
|
||||
num-lanes = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user