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bpf, riscv: Optimize BPF_JMP BPF_K when imm == 0 on RV64
This patch adds an optimization to BPF_JMP (32- and 64-bit) BPF_K for when the BPF immediate is zero. When the immediate is zero, the code can directly use the RISC-V zero register instead of loading a zero immediate to a temporary register first. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Björn Töpel <bjorn.topel@gmail.com> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20200506000320.28965-4-luke.r.nels@gmail.com
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parent
21a099abb7
commit
ca349a6a10
@ -796,7 +796,13 @@ out_be:
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case BPF_JMP32 | BPF_JSET | BPF_K:
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rvoff = rv_offset(i, off, ctx);
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s = ctx->ninsns;
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emit_imm(RV_REG_T1, imm, ctx);
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if (imm) {
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emit_imm(RV_REG_T1, imm, ctx);
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rs = RV_REG_T1;
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} else {
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/* If imm is 0, simply use zero register. */
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rs = RV_REG_ZERO;
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}
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if (!is64) {
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if (is_signed_bpf_cond(BPF_OP(code)))
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emit_sext_32_rd(&rd, ctx);
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@ -811,11 +817,10 @@ out_be:
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if (BPF_OP(code) == BPF_JSET) {
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/* Adjust for and */
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rvoff -= 4;
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emit(rv_and(RV_REG_T1, rd, RV_REG_T1), ctx);
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emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff,
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ctx);
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emit(rv_and(rs, rd, rs), ctx);
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emit_branch(BPF_JNE, rs, RV_REG_ZERO, rvoff, ctx);
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} else {
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emit_branch(BPF_OP(code), rd, RV_REG_T1, rvoff, ctx);
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emit_branch(BPF_OP(code), rd, rs, rvoff, ctx);
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}
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break;
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