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[MIPS] Update/Fix instruction definitions
A small bugfix for up to now unused instruction definitions, and a somewhat larger update to cover MIPS32R2 instructions. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -6,6 +6,7 @@
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* for more details.
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*
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* Copyright (C) 1996, 2000 by Ralf Baechle
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* Copyright (C) 2006 by Thiemo Seufer
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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@ -21,14 +22,14 @@ enum major_op {
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cop0_op, cop1_op, cop2_op, cop1x_op,
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beql_op, bnel_op, blezl_op, bgtzl_op,
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daddi_op, daddiu_op, ldl_op, ldr_op,
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major_1c_op, jalx_op, major_1e_op, major_1f_op,
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spec2_op, jalx_op, mdmx_op, spec3_op,
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lb_op, lh_op, lwl_op, lw_op,
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lbu_op, lhu_op, lwr_op, lwu_op,
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sb_op, sh_op, swl_op, sw_op,
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sdl_op, sdr_op, swr_op, cache_op,
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ll_op, lwc1_op, lwc2_op, pref_op,
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lld_op, ldc1_op, ldc2_op, ld_op,
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sc_op, swc1_op, swc2_op, rdhwr_op,
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sc_op, swc1_op, swc2_op, major_3b_op,
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scd_op, sdc1_op, sdc2_op, sd_op
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};
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@ -37,7 +38,7 @@ enum major_op {
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*/
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enum spec_op {
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sll_op, movc_op, srl_op, sra_op,
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sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
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sllv_op, pmon_op, srlv_op, srav_op,
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jr_op, jalr_op, movz_op, movn_op,
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syscall_op, break_op, spim_op, sync_op,
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mfhi_op, mthi_op, mflo_op, mtlo_op,
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@ -54,6 +55,28 @@ enum spec_op {
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dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
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};
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/*
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* func field of spec2 opcode.
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*/
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enum spec2_op {
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madd_op, maddu_op, mul_op, spec2_3_unused_op,
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msub_op, msubu_op, /* more unused ops */
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clz_op = 0x20, clo_op,
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dclz_op = 0x24, dclo_op,
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sdbpp_op = 0x3f
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};
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/*
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* func field of spec3 opcode.
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*/
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enum spec3_op {
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ext_op, dextm_op, dextu_op, dext_op,
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ins_op, dinsm_op, dinsu_op, dins_op,
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bshfl_op = 0x20,
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dbshfl_op = 0x24,
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rdhwr_op = 0x3f
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};
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/*
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* rt field of bcond opcodes.
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*/
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@ -151,8 +174,8 @@ enum cop1x_func {
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* func field for mad opcodes (MIPS IV).
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*/
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enum mad_func {
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madd_op = 0x08, msub_op = 0x0a,
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nmadd_op = 0x0c, nmsub_op = 0x0e
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madd_fp_op = 0x08, msub_fp_op = 0x0a,
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nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
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};
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/*
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