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dt-bindings: mmc: sprd: Add PHY DLL delay documentation
Introduce some PHY DLL delays properties to help to sample the PHY clock. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -20,6 +20,23 @@ Optional properties:
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- assigned-clocks: the same with "sdio" clock
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- assigned-clock-parents: the default parent of "sdio" clock
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PHY DLL delays are used to delay the data valid window, and align the window
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to sampling clock. PHY DLL delays can be configured by following properties,
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and each property contains 4 cells which are used to configure the clock data
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write line delay value, clock read command line delay value, clock read data
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positive edge delay value and clock read data negative edge delay value.
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Each cell's delay value unit is cycle of the PHY clock.
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- sprd,phy-delay-legacy: Delay value for legacy timing.
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- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
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- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
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- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
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- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
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- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
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- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
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- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
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- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
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Examples:
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sdio0: sdio@20600000 {
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@ -33,6 +50,7 @@ sdio0: sdio@20600000 {
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assigned-clocks = <&ap_clk CLK_EMMC_2X>;
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assigned-clock-parents = <&rpll CLK_RPLL_390M>;
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sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
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bus-width = <8>;
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non-removable;
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no-sdio;
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