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drm/915: fix relaxed tiling on gen2: tile height

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A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Userspace was broken and assumed 8 rows. Chris Wilson noted that the
kernel unfortunately can't reliable check that because libdrm rounds
up the size to the next bucket.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Daniel Vetter 2011-05-12 22:17:20 +01:00 committed by Keith Packard
parent d3bcb75776
commit c8ebc2b076
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/i915/i915_gem.c
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@ -1449,8 +1449,9 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
* edge of an even tile row (where tile rows are counted as if the bo is
* placed in a fenced gtt region).
*/
if (IS_GEN2(dev) ||
(obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
if (IS_GEN2(dev))
tile_height = 16;
else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
tile_height = 32;
else
tile_height = 8;