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drm/radeon: fix bank tiling parameters on evergreen
Handle the 16 bank case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -1986,10 +1986,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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if (rdev->flags & RADEON_IS_IGP)
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rdev->config.evergreen.tile_config |= 1 << 4;
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else {
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if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
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rdev->config.evergreen.tile_config |= 1 << 4;
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else
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switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
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case 0: /* four banks */
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rdev->config.evergreen.tile_config |= 0 << 4;
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break;
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case 1: /* eight banks */
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rdev->config.evergreen.tile_config |= 1 << 4;
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break;
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case 2: /* sixteen banks */
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default:
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rdev->config.evergreen.tile_config |= 2 << 4;
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break;
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}
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}
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rdev->config.evergreen.tile_config |= 0 << 8;
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rdev->config.evergreen.tile_config |=
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