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wifi: rtl8xxxu: Support new chip RTL8188FU
This chip is found in the cheapest USB adapters, e.g. 1.17 USD with VAT and shipping from China included. It's a gen 2 chip, similar to the RTL8723BU, but without Bluetooth. Features: 2.4 GHz, b/g/n mode, 1T1R, 150 Mbps. The vendor driver rtl8188fu version 4.3.23.6_20964.20170110 [0] was used as reference. The CD shipped with the device includes a newer driver, version 5.11.5-1-g12f7cde4b.20201102, but that one couldn't complete the WPA2 key exchange thing for whatever reason. [0] https://github.com/kelebek333/rtl8188fu Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/b14f299d-3248-98fe-eee1-ba50d2e76c74@gmail.com
This commit is contained in:
Bitterblue Smith
Kalle Valo
parent
9695dc2e4b
commit
c888183b21
@ -2,4 +2,4 @@
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obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o
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rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \
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rtl8xxxu_8723a.o rtl8xxxu_8192c.o
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rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o
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@ -35,6 +35,7 @@
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#define REALTEK_USB_CMD_IDX 0x00
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#define TX_TOTAL_PAGE_NUM 0xf8
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#define TX_TOTAL_PAGE_NUM_8188F 0xf7
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#define TX_TOTAL_PAGE_NUM_8192E 0xf3
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#define TX_TOTAL_PAGE_NUM_8723B 0xf7
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/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
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@ -43,6 +44,11 @@
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#define TX_PAGE_NUM_LO_PQ 0x02
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#define TX_PAGE_NUM_NORM_PQ 0x02
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#define TX_PAGE_NUM_PUBQ_8188F 0xe5
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#define TX_PAGE_NUM_HI_PQ_8188F 0x0c
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#define TX_PAGE_NUM_LO_PQ_8188F 0x02
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#define TX_PAGE_NUM_NORM_PQ_8188F 0x02
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#define TX_PAGE_NUM_PUBQ_8192E 0xe7
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#define TX_PAGE_NUM_HI_PQ_8192E 0x08
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#define TX_PAGE_NUM_LO_PQ_8192E 0x0c
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@ -859,6 +865,50 @@ struct rtl8192eu_efuse {
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u8 res12[0xc3];
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};
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struct rtl8188fu_efuse_tx_power {
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u8 cck_base[6];
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u8 ht40_base[5];
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/* a: ofdm; b: ht20 */
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struct rtl8723au_idx ht20_ofdm_1s_diff;
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};
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struct rtl8188fu_efuse {
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__le16 rtl_id;
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u8 res0[0x0e];
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struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */
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u8 res1[0x9c]; /* 0x1c */
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u8 channel_plan; /* 0xb8 */
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u8 xtal_k;
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u8 thermal_meter;
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u8 iqk_lck;
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u8 res2[5];
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u8 rf_board_option;
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u8 rf_feature_option;
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u8 rf_bt_setting;
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u8 eeprom_version;
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u8 eeprom_customer_id;
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u8 res3[2];
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u8 kfree_thermal_k_on;
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u8 rf_antenna_option; /* 0xc9 */
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u8 rfe_option;
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u8 country_code;
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u8 res4[4];
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u8 vid; /* 0xd0 */
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u8 res5[1];
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u8 pid; /* 0xd2 */
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u8 res6[1];
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u8 usb_optional_function;
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u8 res7[2];
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u8 mac_addr[ETH_ALEN]; /* 0xd7 */
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u8 res8[2];
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u8 vendor_name[7];
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u8 res9[2];
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u8 device_name[7]; /* 0xe8 */
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u8 res10[0x41];
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u8 unknown[0x0d]; /* 0x130 */
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u8 res11[0xc3];
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};
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struct rtl8xxxu_reg8val {
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u16 reg;
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u8 val;
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@ -1368,6 +1418,7 @@ struct rtl8xxxu_priv {
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struct rtl8723bu_efuse efuse8723bu;
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struct rtl8192cu_efuse efuse8192;
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struct rtl8192eu_efuse efuse8192eu;
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struct rtl8188fu_efuse efuse8188fu;
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} efuse_wifi;
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u32 adda_backup[RTL8XXXU_ADDA_REGS];
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u32 mac_backup[RTL8XXXU_MAC_REGS];
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@ -1414,6 +1465,7 @@ struct rtl8xxxu_fileops {
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void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
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int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
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void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
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void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv);
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void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
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void (*config_channel) (struct ieee80211_hw *hw);
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int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
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@ -1493,9 +1545,11 @@ int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
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int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
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void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
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void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
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int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data);
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void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
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int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv);
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void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
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void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv);
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int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
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int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
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struct h2c_cmd *h2c, int len);
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@ -1539,7 +1593,9 @@ void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
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u32 rts_rate);
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void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
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u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5);
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void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv);
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extern struct rtl8xxxu_fileops rtl8188fu_fops;
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extern struct rtl8xxxu_fileops rtl8192cu_fops;
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extern struct rtl8xxxu_fileops rtl8192eu_fops;
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extern struct rtl8xxxu_fileops rtl8723au_fops;
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1679
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c
Normal file
1679
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -549,6 +549,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = {
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.llt_init = rtl8xxxu_init_llt_table,
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.init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
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.init_phy_rf = rtl8192cu_init_phy_rf,
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.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
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.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
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.config_channel = rtl8xxxu_gen1_config_channel,
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.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
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@ -1680,6 +1680,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = {
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.llt_init = rtl8xxxu_auto_llt_table,
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.init_phy_bb = rtl8192eu_init_phy_bb,
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.init_phy_rf = rtl8192eu_init_phy_rf,
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.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
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.phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
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.config_channel = rtl8xxxu_gen2_config_channel,
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.parse_rx_desc = rtl8xxxu_parse_rxdesc24,
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@ -366,6 +366,7 @@ struct rtl8xxxu_fileops rtl8723au_fops = {
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.llt_init = rtl8xxxu_init_llt_table,
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.init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
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.init_phy_rf = rtl8723au_init_phy_rf,
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.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
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.phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
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.config_channel = rtl8xxxu_gen1_config_channel,
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.parse_rx_desc = rtl8xxxu_parse_rxdesc16,
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@ -518,7 +518,7 @@ static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
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return ret;
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}
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static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
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void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
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{
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u32 val32;
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@ -1650,6 +1650,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = {
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.init_phy_bb = rtl8723bu_init_phy_bb,
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.init_phy_rf = rtl8723bu_init_phy_rf,
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.phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
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.phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
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.phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
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.config_channel = rtl8xxxu_gen2_config_channel,
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.parse_rx_desc = rtl8xxxu_parse_rxdesc24,
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@ -52,6 +52,7 @@ MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
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MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
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MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
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MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
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MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
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module_param_named(debug, rtl8xxxu_debug, int, 0600);
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MODULE_PARM_DESC(debug, "Set debug mask");
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@ -1606,6 +1607,7 @@ static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
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static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
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{
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const struct usb_device_descriptor *descriptor = &priv->udev->descriptor;
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struct device *dev = &priv->udev->dev;
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struct ieee80211_hw *hw = priv->hw;
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u32 val32, bonding;
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@ -1619,6 +1621,17 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
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return -ENOTSUPP;
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}
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if (descriptor->idVendor == USB_VENDOR_ID_REALTEK &&
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descriptor->idProduct == 0xf179) {
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sprintf(priv->chip_name, "8188FU");
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priv->rtl_chip = RTL8188F;
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priv->rf_paths = 1;
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priv->rx_paths = 1;
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priv->tx_paths = 1;
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priv->has_wifi = 1;
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goto skip_complicated_chip_detection;
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}
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if (val32 & SYS_CFG_BT_FUNC) {
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if (priv->chip_cut >= 3) {
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sprintf(priv->chip_name, "8723BU");
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@ -1685,11 +1698,14 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
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priv->has_wifi = 1;
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}
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skip_complicated_chip_detection:
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hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
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hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
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switch (priv->rtl_chip) {
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case RTL8188E:
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case RTL8188F:
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case RTL8192E:
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case RTL8723B:
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switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
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@ -1720,7 +1736,18 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
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val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
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priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
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val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
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/*
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* 8188FU vendor driver doesn't use REG_NORMAL_SIE_EP_TX,
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* it just decides the queue mapping based on nr_out_eps.
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* However, reading the register returns "0x321" which
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* results in a wrong ep_tx_count of 3 and most frames
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* not being transmitted.
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*/
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if (priv->rtl_chip == RTL8188F)
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val16 = 0;
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else
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val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
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if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
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priv->ep_tx_high_queue = 1;
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priv->ep_tx_count++;
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@ -1763,7 +1790,7 @@ static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
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return 0;
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}
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static int
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int
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rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
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{
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int i;
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@ -1979,7 +2006,7 @@ static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
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/*
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* Init H2C command
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*/
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if (priv->rtl_chip == RTL8723B)
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if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F)
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rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
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exit:
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return ret;
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@ -2099,6 +2126,7 @@ int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
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case 0x88c0:
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case 0x5300:
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case 0x2300:
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case 0x88f0:
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break;
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default:
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ret = -EINVAL;
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@ -2166,7 +2194,9 @@ rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
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}
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}
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if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
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if (priv->rtl_chip != RTL8723B &&
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priv->rtl_chip != RTL8192E &&
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priv->rtl_chip != RTL8188F)
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rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
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return 0;
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@ -3427,7 +3457,7 @@ void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
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priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
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}
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static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
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void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
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{
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u32 val32;
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u32 rf_amode, rf_bmode = 0, lstf;
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@ -4031,6 +4061,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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if (priv->rtl_chip == RTL8192E) {
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rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
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rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
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} else if (priv->rtl_chip == RTL8188F) {
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rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
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rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
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} else {
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/*
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* Enable all interrupts - not obvious USB needs to do this
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@ -4050,11 +4083,25 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
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rtl8xxxu_write32(priv, REG_RCR, val32);
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/*
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* Accept all multicast
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*/
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rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
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rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
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if (priv->rtl_chip == RTL8188F) {
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/* Accept all data frames */
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rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
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/*
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* Since ADF is removed from RCR, ps-poll will not be indicate to driver,
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* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
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*/
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rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
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/* Accept all management frames */
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rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
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} else {
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/*
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* Accept all multicast
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*/
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rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
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rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
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}
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/*
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* Init adaptive controls
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@ -4105,14 +4152,17 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
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rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
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rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
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rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
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if (priv->rtl_chip != RTL8188F)
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/* Firmware will control REG_DRVERLYINT when power saving is enable, */
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/* so don't set this register on STA mode. */
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rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
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rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
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rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
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/*
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* Initialize burst parameters
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*/
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if (priv->rtl_chip == RTL8723B) {
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if (priv->rtl_chip == RTL8723B || priv->rtl_chip == RTL8188F) {
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/*
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* For USB high speed set 512B packets
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*/
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@ -4130,13 +4180,26 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
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rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
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|
||||
rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
|
||||
rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
|
||||
if (priv->rtl_chip == RTL8723B)
|
||||
val8 = 0x5e;
|
||||
else if (priv->rtl_chip == RTL8188F)
|
||||
val8 = 0x70; /* 0x5e would make it very slow */
|
||||
rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, val8);
|
||||
rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
|
||||
rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
|
||||
rtl8xxxu_write8(priv, REG_PIFS, 0x00);
|
||||
rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
|
||||
rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
|
||||
if (priv->rtl_chip == RTL8188F) {
|
||||
rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
|
||||
rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
|
||||
}
|
||||
if (priv->rtl_chip == RTL8723B)
|
||||
val8 = 0x50;
|
||||
else if (priv->rtl_chip == RTL8188F)
|
||||
val8 = 0x28; /* 0x50 would make the upload slow */
|
||||
rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, val8);
|
||||
rtl8xxxu_write8(priv, REG_USTIME_EDCA, val8);
|
||||
|
||||
/* to prevent mac is reseted by bus. */
|
||||
val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
|
||||
val8 |= BIT(5) | BIT(6);
|
||||
rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
|
||||
@ -4145,6 +4208,11 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
|
||||
if (fops->init_aggregation)
|
||||
fops->init_aggregation(priv);
|
||||
|
||||
if (priv->rtl_chip == RTL8188F) {
|
||||
rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
|
||||
rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable CCK and OFDM block
|
||||
*/
|
||||
@ -4163,7 +4231,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
|
||||
fops->set_tx_power(priv, 1, false);
|
||||
|
||||
/* Let the 8051 take control of antenna setting */
|
||||
if (priv->rtl_chip != RTL8192E) {
|
||||
if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F) {
|
||||
val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
|
||||
val8 |= LEDCFG2_DPDT_SELECT;
|
||||
rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
|
||||
@ -4174,7 +4242,8 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
|
||||
/* Disable BAR - not sure if this has any effect on USB */
|
||||
rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
|
||||
|
||||
rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
|
||||
if (priv->rtl_chip != RTL8188F)
|
||||
rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
|
||||
|
||||
if (fops->init_statistics)
|
||||
fops->init_statistics(priv);
|
||||
@ -4191,20 +4260,38 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
|
||||
* Reset USB mode switch setting
|
||||
*/
|
||||
rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
|
||||
} else if (priv->rtl_chip == RTL8188F) {
|
||||
/*
|
||||
* Init GPIO settings for 8188f
|
||||
*/
|
||||
val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
|
||||
val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
|
||||
rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
|
||||
}
|
||||
|
||||
rtl8723a_phy_lc_calibrate(priv);
|
||||
if (priv->rtl_chip == RTL8188F)
|
||||
/* CCK PD */
|
||||
rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
|
||||
|
||||
fops->phy_lc_calibrate(priv);
|
||||
|
||||
fops->phy_iq_calibrate(priv);
|
||||
|
||||
/*
|
||||
* This should enable thermal meter
|
||||
*/
|
||||
if (fops->gen2_thermal_meter)
|
||||
rtl8xxxu_write_rfreg(priv,
|
||||
RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
|
||||
else
|
||||
if (fops->gen2_thermal_meter) {
|
||||
if (priv->rtl_chip == RTL8188F) {
|
||||
val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
|
||||
val32 |= 0x30000;
|
||||
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
|
||||
} else {
|
||||
rtl8xxxu_write_rfreg(priv,
|
||||
RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
|
||||
}
|
||||
} else {
|
||||
rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
|
||||
}
|
||||
|
||||
/* Set NAV_UPPER to 30000us */
|
||||
val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
|
||||
@ -6674,6 +6761,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
|
||||
case 0x8178:
|
||||
case 0x817f:
|
||||
case 0x818b:
|
||||
case 0xf179:
|
||||
untested = 0;
|
||||
break;
|
||||
}
|
||||
@ -6886,6 +6974,9 @@ static const struct usb_device_id dev_table[] = {
|
||||
.driver_info = (unsigned long)&rtl8723bu_fops},
|
||||
{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
|
||||
.driver_info = (unsigned long)&rtl8723bu_fops},
|
||||
/* RTL8188FU */
|
||||
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
|
||||
.driver_info = (unsigned long)&rtl8188fu_fops},
|
||||
#ifdef CONFIG_RTL8XXXU_UNTESTED
|
||||
/* Still supported by rtlwifi */
|
||||
{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
|
||||
|
||||
@ -135,6 +135,7 @@
|
||||
#define REG_CAL_TIMER 0x003c
|
||||
#define REG_ACLK_MON 0x003e
|
||||
#define REG_GPIO_MUXCFG 0x0040
|
||||
#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
|
||||
#define REG_GPIO_IO_SEL 0x0042
|
||||
#define REG_MAC_PINMUX_CFG 0x0043
|
||||
#define REG_GPIO_PIN_CTRL 0x0044
|
||||
@ -391,6 +392,7 @@
|
||||
#define REG_CPWM 0x012f
|
||||
#define REG_FWIMR 0x0130
|
||||
#define REG_FWISR 0x0134
|
||||
#define REG_FTIMR 0x0138
|
||||
#define REG_PKTBUF_DBG_CTRL 0x0140
|
||||
#define REG_PKTBUF_DBG_DATA_L 0x0144
|
||||
#define REG_PKTBUF_DBG_DATA_H 0x0148
|
||||
@ -440,6 +442,9 @@
|
||||
|
||||
#define REG_FIFOPAGE 0x0204
|
||||
#define REG_TDECTRL 0x0208
|
||||
|
||||
#define REG_DWBCN0_CTRL_8188F REG_TDECTRL
|
||||
|
||||
#define REG_TXDMA_OFFSET_CHK 0x020c
|
||||
#define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
|
||||
#define REG_TXDMA_STATUS 0x0210
|
||||
@ -925,6 +930,7 @@
|
||||
|
||||
#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */
|
||||
#define REG_FPGA0_XB_LSSI_READBACK 0x08a4
|
||||
#define REG_FPGA0_PSD_REPORT 0x08b4
|
||||
#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */
|
||||
#define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */
|
||||
|
||||
@ -936,6 +942,7 @@
|
||||
#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
|
||||
#define REG_RFE_BUFFER 0x0944 /* 8723BU */
|
||||
#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */
|
||||
#define REG_OFDM_RX_DFIR 0x954
|
||||
|
||||
#define REG_CCK0_SYSTEM 0x0a00
|
||||
#define CCK0_SIDEBAND BIT(4)
|
||||
@ -946,6 +953,13 @@
|
||||
#define CCK0_AFE_RX_ANT_A 0
|
||||
#define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
|
||||
|
||||
#define REG_CCK_PD_THRESH 0x0a0a
|
||||
#define CCK_PD_TYPE1_LV0_TH 0x40
|
||||
#define CCK_PD_TYPE1_LV1_TH 0x83
|
||||
#define CCK_PD_TYPE1_LV2_TH 0xcd
|
||||
#define CCK_PD_TYPE1_LV3_TH 0xdd
|
||||
#define CCK_PD_TYPE1_LV4_TH 0xed
|
||||
|
||||
#define REG_CONFIG_ANT_A 0x0b68
|
||||
#define REG_CONFIG_ANT_B 0x0b6c
|
||||
|
||||
@ -965,6 +979,7 @@
|
||||
|
||||
#define REG_OFDM0_FA_RSTC 0x0c0c
|
||||
|
||||
#define REG_OFDM0_XA_RX_AFE 0x0c10
|
||||
#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
|
||||
#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
|
||||
|
||||
@ -1011,6 +1026,9 @@
|
||||
#define OFDM_LSTF_MASK 0x70000000
|
||||
|
||||
#define REG_OFDM1_TRX_PATH_ENABLE 0x0d04
|
||||
#define REG_OFDM1_CFO_TRACKING 0x0d2c
|
||||
#define REG_OFDM1_CSI_FIX_MASK1 0x0d40
|
||||
#define REG_OFDM1_CSI_FIX_MASK2 0x0d44
|
||||
|
||||
#define REG_TX_AGC_A_RATE18_06 0x0e00
|
||||
#define REG_TX_AGC_A_RATE54_24 0x0e04
|
||||
@ -1202,6 +1220,7 @@
|
||||
#define RF6052_REG_UNKNOWN_43 0x43
|
||||
#define RF6052_REG_UNKNOWN_55 0x55
|
||||
#define RF6052_REG_UNKNOWN_56 0x56
|
||||
#define RF6052_REG_RXG_MIX_SWBW 0x87
|
||||
#define RF6052_REG_S0S1 0xb0
|
||||
#define RF6052_REG_UNKNOWN_DF 0xdf
|
||||
#define RF6052_REG_UNKNOWN_ED 0xed
|
||||
|
||||
Loading…
Reference in New Issue
Block a user