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Merge branch '85xx' into for_paulus
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commit
c86c676cca
@ -208,7 +208,7 @@ EXPORT_SYMBOL(mmu_hash_lock); /* For MOL */
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extern long *intercept_table;
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EXPORT_SYMBOL(intercept_table);
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#endif /* CONFIG_PPC_STD_MMU_32 */
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#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
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#ifdef CONFIG_PPC_DCR_NATIVE
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EXPORT_SYMBOL(__mtdcr);
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EXPORT_SYMBOL(__mfdcr);
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#endif
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@ -5,7 +5,8 @@ endif
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obj-$(CONFIG_MPIC) += mpic.o
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obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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obj-$(CONFIG_PPC_MPC106) += grackle.o
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obj-$(CONFIG_PPC_DCR) += dcr.o dcr-low.o
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obj-$(CONFIG_PPC_DCR) += dcr.o
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obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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@ -20,8 +20,7 @@
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#ifndef _ASM_POWERPC_DCR_NATIVE_H
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#define _ASM_POWERPC_DCR_NATIVE_H
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#ifdef __KERNEL__
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#include <asm/reg.h>
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#ifndef __ASSEMBLY__
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typedef struct {} dcr_host_t;
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@ -32,7 +31,41 @@ typedef struct {} dcr_host_t;
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#define dcr_read(host, dcr_n) mfdcr(dcr_n)
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#define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value)
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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unsigned int __mfdcr(int reg);
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#define mfdcr(rn) \
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({unsigned int rval; \
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if (__builtin_constant_p(rn)) \
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asm volatile("mfdcr %0," __stringify(rn) \
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: "=r" (rval)); \
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else \
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rval = __mfdcr(rn); \
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rval;})
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#define mtdcr(rn, v) \
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do { \
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if (__builtin_constant_p(rn)) \
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asm volatile("mtdcr " __stringify(rn) ",%0" \
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: : "r" (v)); \
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else \
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__mtdcr(rn, v); \
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} while (0)
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/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
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#define mfdcri(base, reg) \
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({ \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mfdcr(base ## _CFGDATA); \
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})
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#define mtdcri(base, reg, data) \
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do { \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mtdcr(base ## _CFGDATA, data); \
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} while (0)
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_NATIVE_H */
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@ -20,6 +20,7 @@
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#ifndef _ASM_POWERPC_DCR_H
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#define _ASM_POWERPC_DCR_H
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC_DCR
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#ifdef CONFIG_PPC_DCR_NATIVE
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#include <asm/dcr-native.h>
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@ -38,5 +39,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
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unsigned int index);
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#endif /* CONFIG_PPC_MERGE */
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#endif /* CONFIG_PPC_DCR */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_DCR_H */
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@ -9,41 +9,9 @@
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#ifndef __ASM_PPC_REG_BOOKE_H__
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#define __ASM_PPC_REG_BOOKE_H__
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#include <asm/dcr.h>
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#ifndef __ASSEMBLY__
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/* Device Control Registers */
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void __mtdcr(int reg, unsigned int val);
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unsigned int __mfdcr(int reg);
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#define mfdcr(rn) \
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({unsigned int rval; \
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if (__builtin_constant_p(rn)) \
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asm volatile("mfdcr %0," __stringify(rn) \
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: "=r" (rval)); \
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else \
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rval = __mfdcr(rn); \
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rval;})
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#define mtdcr(rn, v) \
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do { \
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if (__builtin_constant_p(rn)) \
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asm volatile("mtdcr " __stringify(rn) ",%0" \
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: : "r" (v)); \
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else \
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__mtdcr(rn, v); \
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} while (0)
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/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
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#define mfdcri(base, reg) \
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({ \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mfdcr(base ## _CFGDATA); \
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})
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#define mtdcri(base, reg, data) \
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do { \
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mtdcr(base ## _CFGADDR, base ## _ ## reg); \
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mtdcr(base ## _CFGDATA, data); \
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} while (0)
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile("mfpmr %0," __stringify(rn) \
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