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drm/amd/sriov skip vcn powergating and dec_ring_test
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct register read/write. 2.Skip powergating configuration in hw fini because VCN3.0 SRIOV doesn't support powergating. V2: delete unneccessary white lines and refine implementation. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -421,6 +421,10 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
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unsigned i;
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int r;
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/* VCN in SRIOV does not support direct register read/write */
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if (amdgpu_sriov_vf(adev))
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return 0;
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WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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@ -354,11 +354,13 @@ static int vcn_v3_0_hw_fini(void *handle)
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ring = &adev->vcn.inst[i].ring_dec;
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if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
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(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(VCN, i, mmUVD_STATUS)))
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vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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if (!amdgpu_sriov_vf(adev)) {
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if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
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(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
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RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
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vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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}
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}
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ring->sched.ready = false;
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for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
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@ -1861,6 +1863,15 @@ static int vcn_v3_0_set_powergating_state(void *handle,
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret;
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/* for SRIOV, guest should not control VCN Power-gating
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* MMSCH FW should control Power-gating and clock-gating
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* guest should avoid touching CGC and PG
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*/
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if (amdgpu_sriov_vf(adev)) {
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adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
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return 0;
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}
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if(state == adev->vcn.cur_state)
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return 0;
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