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drm/amdgpu: add psp support for navy_flounder
Currently skip ASD FW loading and ih reroute per sienna_cichlid. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -99,6 +99,7 @@ static int psp_early_init(void *handle)
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case CHIP_NAVI14:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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psp_v11_0_set_psp_funcs(psp);
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psp->autoload_supported = true;
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break;
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@ -498,7 +499,9 @@ static int psp_asd_load(struct psp_context *psp)
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* add workaround to bypass it for sriov now.
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* TODO: add version check to make it common
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*/
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if (amdgpu_sriov_vf(psp->adev) || (psp->adev->asic_type == CHIP_SIENNA_CICHLID))
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if (amdgpu_sriov_vf(psp->adev) ||
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(psp->adev->asic_type == CHIP_SIENNA_CICHLID) ||
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(psp->adev->asic_type == CHIP_NAVY_FLOUNDER))
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return 0;
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cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
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@ -1763,7 +1766,8 @@ static int psp_np_fw_load(struct psp_context *psp)
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continue;
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if (psp->autoload_supported &&
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adev->asic_type == CHIP_SIENNA_CICHLID &&
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(adev->asic_type == CHIP_SIENNA_CICHLID ||
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adev->asic_type == CHIP_NAVY_FLOUNDER) &&
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(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
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ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
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ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
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@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
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MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
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MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
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MODULE_FIRMWARE("amdgpu/sienna_cichlid_asd.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin");
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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@ -100,6 +102,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
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case CHIP_SIENNA_CICHLID:
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chip_name = "sienna_cichlid";
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break;
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case CHIP_NAVY_FLOUNDER:
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chip_name = "navy_flounder";
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break;
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default:
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BUG();
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}
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@ -108,7 +113,8 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
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if (err)
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return err;
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if (adev->asic_type != CHIP_SIENNA_CICHLID) {
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if (adev->asic_type != CHIP_SIENNA_CICHLID &&
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adev->asic_type != CHIP_NAVY_FLOUNDER) {
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err = psp_init_asd_microcode(psp, chip_name);
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if (err)
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return err;
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@ -173,6 +179,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
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}
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break;
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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break;
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default:
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BUG();
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@ -397,7 +404,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
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struct amdgpu_device *adev = psp->adev;
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if ((!amdgpu_sriov_vf(adev)) &&
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(adev->asic_type != CHIP_SIENNA_CICHLID))
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(adev->asic_type != CHIP_SIENNA_CICHLID) &&
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(adev->asic_type != CHIP_NAVY_FLOUNDER))
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psp_v11_0_reroute_ih(psp);
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ring = &psp->km_ring;
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