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Documentation: sound: add description of Intel HDaudio multi-links
Add description of 'Skylake' multi-link structure added in 2015 and recent extensions to support SoundWire/DMIC/SSP interfaces. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Link: https://lore.kernel.org/r/20230404104127.5629-2-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pierre-Louis Bossart
Mark Brown
parent
8a0cfac697
commit
c7a92574ec
@ -9,3 +9,4 @@ HD-Audio
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controls
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dp-mst
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realtek-pc-beep
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intel-multi-link
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312
Documentation/sound/hd-audio/intel-multi-link.rst
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312
Documentation/sound/hd-audio/intel-multi-link.rst
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@ -0,0 +1,312 @@
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.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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.. include:: <isonum.txt>
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================================================
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HDAudio multi-link extensions on Intel platforms
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================================================
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:Copyright: |copy| 2023 Intel Corporation
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This file documents the 'multi-link structure' introduced in 2015 with
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the Skylake processor and recently extended in newer Intel platforms
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HDaudio existing link mapping (2015 addition in SkyLake)
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========================================================
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External HDAudio codecs are handled with link #0, while iDISP codec
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for HDMI/DisplayPort is handled with link #1.
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The only change to the 2015 definitions is the declaration of the
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LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
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backwards-compatible change.
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LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They
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are only used in existing drivers when the SCF value needs to be
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corrected.
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Basic structure for HDaudio codecs
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----------------------------------
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::
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+-----------+
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| ML cap #0 |
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+-----------+
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| ML cap #1 |---+
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+-----------+ |
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+--> 0x0 +---------------+ LCAP
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| ALT=0 |
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+---------------+
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| S192 |
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+---------------+
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| S96 |
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+---------------+
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| S48 |
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+---------------+
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| S24 |
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+---------------+
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| S12 |
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+---------------+
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| S6 |
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+---------------+
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0x4 +---------------+ LCTL
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| INTSTS |
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+---------------+
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| CPA |
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+---------------+
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| SPA |
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+---------------+
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| SCF |
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+---------------+
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0x8 +---------------+ LOSIDV
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| L1OSIVD15 |
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+---------------+
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| L1OSIDV.. |
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+---------------+
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| L1OSIDV1 |
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+---------------+
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0xC +---------------+ LSDIID
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| SDIID14 |
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+---------------+
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| SDIID... |
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+---------------+
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| SDIID0 |
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+---------------+
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SoundWire HDaudio extended link mapping
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=======================================
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A SoundWire extended link is identified when LCAP.ALT=1 and
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LEPTR.ID=0.
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DMA control uses the existing LOSIDV register.
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Changes include additional descriptions for enumeration that were not
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present in earlier generations.
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- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
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- number of sublinks (manager IP) in LCAP.LSCOUNT
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- power management moved from SHIM to LCTL.SPA bits
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- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
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- mapping of SoundWire codecs to SDI ID bits
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- move of SHIM and Cadence registers to different offsets, with no
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change in functionality. The LEPTR.PTR value is an offset from the
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ML address, with a default value of 0x30000.
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Extended structure for SoundWire (assuming 4 Manager IP)
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--------------------------------------------------------
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::
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+-----------+
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| ML cap #0 |
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+-----------+
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| ML cap #1 |
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+-----------+
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| ML cap #2 |---+
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+-----------+ |
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|
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+--> 0x0 +---------------+ LCAP
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| ALT=1 |
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+---------------+
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| INTC |
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+---------------+
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| OFLS |
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+---------------+
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| LSS |
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+---------------+
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| SLCOUNT=4 |-----------+
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+---------------+ |
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|
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0x4 +---------------+ LCTL |
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| INTSTS | |
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+---------------+ |
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| CPA (x bits) | |
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+---------------+ |
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| SPA (x bits) | |
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+---------------+ for each sublink x
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| INTEN | |
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+---------------+ |
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| OFLEN | |
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+---------------+ |
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|
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0x8 +---------------+ LOSIDV |
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| L1OSIVD15 | |
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+---------------+ |
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| L1OSIDV.. | |
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+---------------+ |
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| L1OSIDV1 | +---+----------------------------------------------------------+
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+---------------+ | |
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v |
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0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 |
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| SDIID14 | | | SoundWire SHIM | |
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+---------------+ | | generic | |
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| SDIID... | | +-----------------+ 0x00030100 |
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+---------------+ | | SoundWire IP | |
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| SDIID0 | | +-----------------+ 0x00036000 |
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+---------------+ | | SoundWire SHIM | |
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| | vendor-specific | |
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0x1C +---------------+ LSYNC | +-----------------+ |
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| CMDSYNC | | v
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+---------------+ | +-----------------+ 0x00030000 + 0x8000 * x
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| SYNCGO | | | SoundWire SHIM |
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+---------------+ | | generic |
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| SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x
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+---------------+ | | SoundWire IP |
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| SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x
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+---------------+ | | SoundWire SHIM |
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| | vendor-specific |
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0x20 +---------------+ LEPTR | +-----------------+
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| ID = 0 | |
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+---------------+ |
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| VER | |
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+---------------+ |
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| PTR |------------+
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+---------------+
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DMIC HDaudio extended link mapping
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==================================
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A DMIC extended link is identified when LCAP.ALT=1 and
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LEPTR.ID=0xC1 are set.
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DMA control uses the existing LOSIDV register
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Changes include additional descriptions for enumeration that were not
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present in earlier generations.
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- multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
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- power management with LCTL.SPA bits
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- hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
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- move of DMIC registers to different offsets, with no change in
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functionality. The LEPTR.PTR value is an offset from the ML
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address, with a default value of 0x10000.
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Extended structure for DMIC
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---------------------------
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::
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+-----------+
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| ML cap #0 |
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+-----------+
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| ML cap #1 |
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+-----------+
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| ML cap #2 |---+
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+-----------+ |
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+--> 0x0 +---------------+ LCAP
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| ALT=1 |
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+---------------+
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| INTC |
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+---------------+
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| OFLS |
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+---------------+
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| SLCOUNT=1 |
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+---------------+
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0x4 +---------------+ LCTL
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| INTSTS |
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+---------------+
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| CPA |
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+---------------+
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| SPA |
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+---------------+
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| INTEN |
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+---------------+
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| OFLEN |
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+---------------+ +---> 0x10000 +-----------------+ 0x00010000
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| | DMIC SHIM |
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0x8 +---------------+ LOSIDV | | generic |
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| L1OSIVD15 | | +-----------------+ 0x00010100
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+---------------+ | | DMIC IP |
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| L1OSIDV.. | | +-----------------+ 0x00016000
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+---------------+ | | DMIC SHIM |
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| L1OSIDV1 | | | vendor-specific |
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+---------------+ | +-----------------+
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0x20 +---------------+ LEPTR |
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| ID = 0xC1 | |
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+---------------+ |
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| VER | |
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+---------------+ |
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| PTR |-----------+
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+---------------+
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SSP HDaudio extended link mapping
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=================================
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A DMIC extended link is identified when LCAP.ALT=1 and
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LEPTR.ID=0xC0 are set.
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DMA control uses the existing LOSIDV register
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Changes include additional descriptions for enumeration and control that were not
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present in earlier generations:
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- number of sublinks (SSP IP instances) in LCAP.LSCOUNT
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- power management moved from SHIM to LCTL.SPA bits
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- hand-over to the DSP for access to multi-link registers, SHIM/IP
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with LCTL.OFLEN
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- move of SHIM and SSP IP registers to different offsets, with no
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change in functionality. The LEPTR.PTR value is an offset from the ML
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address, with a default value of 0x28000.
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Extended structure for SSP (assuming 3 instances of the IP)
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-----------------------------------------------------------
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::
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+-----------+
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| ML cap #0 |
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+-----------+
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| ML cap #1 |
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+-----------+
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| ML cap #2 |---+
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+-----------+ |
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+--> 0x0 +---------------+ LCAP
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| ALT=1 |
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+---------------+
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| INTC |
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+---------------+
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| OFLS |
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+---------------+
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| SLCOUNT=3 |-------------------------for each sublink x -------------------------+
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+---------------+ |
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0x4 +---------------+ LCTL |
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| INTSTS | |
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+---------------+ |
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| CPA (x bits) | |
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+---------------+ |
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| SPA (x bits) | |
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+---------------+ |
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| INTEN | |
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+---------------+ |
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| OFLEN | |
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+---------------+ +---> 0x28000 +-----------------+ 0x00028000 |
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| | SSP SHIM | |
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0x8 +---------------+ LOSIDV | | generic | |
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| L1OSIVD15 | | +-----------------+ 0x00028100 |
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+---------------+ | | SSP IP | |
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| L1OSIDV.. | | +-----------------+ 0x00028C00 |
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+---------------+ | | SSP SHIM | |
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| L1OSIDV1 | | | vendor-specific | |
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+---------------+ | +-----------------+ |
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| v
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0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x
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| ID = 0xC0 | | | SSP SHIM |
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+---------------+ | | generic |
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| VER | | +-----------------+ 0x00028100 + 0x1000 * x
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+---------------+ | | SSP IP |
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| PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x
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+---------------+ | SSP SHIM |
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| vendor-specific |
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+-----------------+
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