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PCI: tegra: Add Tegra210 support

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The PCIe host controller found on Tegra X1 is very similar to its
predecessor on Tegra K1. A bug was introduced in the new revision that
is worked around by always enabling the performance counter, otherwise
accesses to configuration space will block for a number of seconds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
This commit is contained in:
Thierry Reding 2016-11-25 11:57:15 +01:00 committed by Bjorn Helgaas
parent 76245ca2df
commit c7a091c762
1 changed files with 34 additions and 8 deletions
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42
drivers/pci/host/pci-tegra.c
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@ -51,10 +51,6 @@
#include <soc/tegra/cpuidle.h> #include <soc/tegra/cpuidle.h>
#include <soc/tegra/pmc.h> #include <soc/tegra/pmc.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>
#define INT_PCI_MSI_NR (8 * 32) #define INT_PCI_MSI_NR (8 * 32)
/* register definitions */ /* register definitions */
@ -384,8 +380,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
unsigned int busnr) unsigned int busnr)
{ {
struct device *dev = pcie->dev; struct device *dev = pcie->dev;
pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | pgprot_t prot = pgprot_device(PAGE_KERNEL);
L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED);
phys_addr_t cs = pcie->cs->start; phys_addr_t cs = pcie->cs->start;
struct tegra_pcie_bus *bus; struct tegra_pcie_bus *bus;
unsigned int i; unsigned int i;
@ -1612,7 +1607,8 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
struct device *dev = pcie->dev; struct device *dev = pcie->dev;
struct device_node *np = dev->of_node; struct device_node *np = dev->of_node;
if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
switch (lanes) { switch (lanes) {
case 0x0000104: case 0x0000104:
dev_info(dev, "4x1, 1x1 configuration\n"); dev_info(dev, "4x1, 1x1 configuration\n");
@ -1733,7 +1729,22 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
struct device_node *np = dev->of_node; struct device_node *np = dev->of_node;
unsigned int i = 0; unsigned int i = 0;
if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
pcie->num_supplies = 6;
pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
sizeof(*pcie->supplies),
GFP_KERNEL);
if (!pcie->supplies)
return -ENOMEM;
pcie->supplies[i++].supply = "avdd-pll-uerefe";
pcie->supplies[i++].supply = "hvddio-pex";
pcie->supplies[i++].supply = "dvddio-pex";
pcie->supplies[i++].supply = "dvdd-pex-pll";
pcie->supplies[i++].supply = "hvdd-pex-pll-e";
pcie->supplies[i++].supply = "vddio-pex-ctl";
} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
pcie->num_supplies = 7; pcie->num_supplies = 7;
pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
@ -2088,7 +2099,22 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.force_pca_enable = false, .force_pca_enable = false,
}; };
static const struct tegra_pcie_soc tegra210_pcie = {
.num_ports = 2,
.msi_base_shift = 8,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x90b890b8,
.has_pex_clkreq_en = true,
.has_pex_bias_ctrl = true,
.has_intr_prsnt_sense = true,
.has_cml_clk = true,
.has_gen2 = true,
.force_pca_enable = true,
};
static const struct of_device_id tegra_pcie_of_match[] = { static const struct of_device_id tegra_pcie_of_match[] = {
{ .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
{ .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie }, { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie }, { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
{ .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie }, { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },