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ARM: proc-v7: sanitise and document registers around errata
Document that r13 is not a stack in the initialisation function, in case anyone gets other ideas. Document the registers available for the errata workarounds, and specifically which registers contain parts of the MIDR register, as well as which registers must be preserved. Lastly, use the lowest numbered available register (r0) rather than r10 for temporary storage. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
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4419496884
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c76f238e26
@ -252,7 +252,7 @@ ENDPROC(cpu_pj4b_do_resume)
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* r1, r2, r4, r5, r9 must be preserved.
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* r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
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* r4: TTBR0 (low word)
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* r5: TTBR0 (high word if LPAE)
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* r8: TTBR1
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@ -285,57 +285,65 @@ __v7_ca17mp_setup:
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#endif
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b __v7_setup
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/*
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* Errata:
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* r0, r10 available for use
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* r1, r2, r4, r5, r9, r13: must be preserved
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* r3: contains MIDR rX number in bits 23-20
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* r6: contains MIDR rXpY as 8-bit XY number
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* r9: MIDR
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*/
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__ca8_errata:
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#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
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teq r3, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
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orreq r0, r0, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
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orreq r0, r0, #(1 << 5) @ set L1NEON to 1
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orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r0, #1 << 22
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orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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b __errata_finish
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__ca9_errata:
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 @ only present up to r2p2
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mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrle r10, r10, #1 << 4 @ set bit #4
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mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
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mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orrle r0, r0, #1 << 4 @ set bit #4
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mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_742231
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 12 @ set bit #12
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orreq r10, r10, #1 << 22 @ set bit #22
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orreq r0, r0, #1 << 12 @ set bit #12
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orreq r0, r0, #1 << 22 @ set bit #22
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mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r3, #0x00200000 @ only present in r2p*
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orreq r0, r0, #1 << 6 @ set bit #6
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mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
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ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
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ALT_UP_B(1f)
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mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrlt r10, r10, #1 << 11 @ set bit #11
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mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
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mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orrlt r0, r0, #1 << 11 @ set bit #11
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mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
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1:
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#endif
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b __errata_finish
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@ -343,9 +351,9 @@ __ca9_errata:
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__ca15_errata:
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#ifdef CONFIG_ARM_ERRATA_773022
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cmp r6, #0x4 @ only present up to r0p4
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mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
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orrle r10, r10, #1 << 1 @ disable loop buffer
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mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
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mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
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orrle r0, r0, #1 << 1 @ disable loop buffer
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mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
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#endif
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b __errata_finish
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@ -409,8 +417,8 @@ __v7_setup:
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bl v7_flush_dcache_louis
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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and r10, r9, #0xff000000 @ ARM?
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teq r10, #0x41000000
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and r0, r9, #0xff000000 @ ARM?
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teq r0, #0x41000000
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bne __errata_finish
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and r3, r9, #0x00f00000 @ variant
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and r6, r9, #0x0000000f @ revision
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