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pinctrl: qcom: Add IPQ9574 pinctrl driver
Add pinctrl definitions for the TLMM of IPQ9574 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Devi Priya
Linus Walleij
parent
5b63ccb69e
commit
c74eef68fd
@ -80,6 +80,17 @@ config PINCTRL_IPQ6018
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Qualcomm Technologies Inc. IPQ6018 platform. Select this for
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IPQ6018.
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config PINCTRL_IPQ9574
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tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
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depends on OF || COMPILE_TEST
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depends on ARM64 || COMPILE_TEST
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depends on PINCTRL_MSM
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for
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the Qualcomm Technologies Inc. TLMM block found on the
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Qualcomm Technologies Inc. IPQ9574 platform. Select this for
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IPQ9574.
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config PINCTRL_MSM8226
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tristate "Qualcomm 8226 pin controller driver"
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depends on OF
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@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
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obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
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obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
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obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
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obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
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obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
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obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
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obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
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826
drivers/pinctrl/qcom/pinctrl-ipq9574.c
Normal file
826
drivers/pinctrl/qcom/pinctrl-ipq9574.c
Normal file
@ -0,0 +1,826 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright (c) 2023 The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-msm.h"
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#define FUNCTION(fname) \
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[msm_mux_##fname] = { \
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.name = #fname, \
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.groups = fname##_groups, \
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.ngroups = ARRAY_SIZE(fname##_groups), \
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}
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#define REG_SIZE 0x1000
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#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
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{ \
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.name = "gpio" #id, \
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.pins = gpio##id##_pins, \
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.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
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.funcs = (int[]){ \
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msm_mux_gpio, /* gpio mode */ \
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msm_mux_##f1, \
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msm_mux_##f2, \
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msm_mux_##f3, \
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msm_mux_##f4, \
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msm_mux_##f5, \
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msm_mux_##f6, \
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msm_mux_##f7, \
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msm_mux_##f8, \
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msm_mux_##f9 \
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}, \
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.nfuncs = 10, \
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.ctl_reg = REG_SIZE * id, \
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.io_reg = 0x4 + REG_SIZE * id, \
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.intr_cfg_reg = 0x8 + REG_SIZE * id, \
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.intr_status_reg = 0xc + REG_SIZE * id, \
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.intr_target_reg = 0x8 + REG_SIZE * id, \
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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.intr_enable_bit = 0, \
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.intr_status_bit = 0, \
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.intr_target_bit = 5, \
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.intr_target_kpss_val = 3, \
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.intr_raw_status_bit = 4, \
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.intr_polarity_bit = 1, \
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.intr_detection_bit = 2, \
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.intr_detection_width = 2, \
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}
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static const struct pinctrl_pin_desc ipq9574_pins[] = {
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PINCTRL_PIN(0, "GPIO_0"),
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PINCTRL_PIN(1, "GPIO_1"),
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PINCTRL_PIN(2, "GPIO_2"),
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PINCTRL_PIN(3, "GPIO_3"),
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PINCTRL_PIN(4, "GPIO_4"),
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PINCTRL_PIN(5, "GPIO_5"),
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PINCTRL_PIN(6, "GPIO_6"),
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PINCTRL_PIN(7, "GPIO_7"),
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PINCTRL_PIN(8, "GPIO_8"),
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PINCTRL_PIN(9, "GPIO_9"),
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PINCTRL_PIN(10, "GPIO_10"),
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PINCTRL_PIN(11, "GPIO_11"),
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PINCTRL_PIN(12, "GPIO_12"),
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PINCTRL_PIN(13, "GPIO_13"),
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PINCTRL_PIN(14, "GPIO_14"),
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PINCTRL_PIN(15, "GPIO_15"),
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PINCTRL_PIN(16, "GPIO_16"),
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PINCTRL_PIN(17, "GPIO_17"),
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PINCTRL_PIN(18, "GPIO_18"),
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PINCTRL_PIN(19, "GPIO_19"),
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PINCTRL_PIN(20, "GPIO_20"),
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PINCTRL_PIN(21, "GPIO_21"),
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PINCTRL_PIN(22, "GPIO_22"),
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PINCTRL_PIN(23, "GPIO_23"),
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PINCTRL_PIN(24, "GPIO_24"),
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PINCTRL_PIN(25, "GPIO_25"),
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PINCTRL_PIN(26, "GPIO_26"),
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PINCTRL_PIN(27, "GPIO_27"),
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PINCTRL_PIN(28, "GPIO_28"),
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PINCTRL_PIN(29, "GPIO_29"),
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PINCTRL_PIN(30, "GPIO_30"),
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PINCTRL_PIN(31, "GPIO_31"),
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PINCTRL_PIN(32, "GPIO_32"),
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PINCTRL_PIN(33, "GPIO_33"),
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PINCTRL_PIN(34, "GPIO_34"),
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PINCTRL_PIN(35, "GPIO_35"),
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PINCTRL_PIN(36, "GPIO_36"),
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PINCTRL_PIN(37, "GPIO_37"),
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PINCTRL_PIN(38, "GPIO_38"),
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PINCTRL_PIN(39, "GPIO_39"),
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PINCTRL_PIN(40, "GPIO_40"),
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PINCTRL_PIN(41, "GPIO_41"),
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PINCTRL_PIN(42, "GPIO_42"),
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PINCTRL_PIN(43, "GPIO_43"),
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PINCTRL_PIN(44, "GPIO_44"),
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PINCTRL_PIN(45, "GPIO_45"),
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PINCTRL_PIN(46, "GPIO_46"),
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PINCTRL_PIN(47, "GPIO_47"),
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PINCTRL_PIN(48, "GPIO_48"),
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PINCTRL_PIN(49, "GPIO_49"),
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PINCTRL_PIN(50, "GPIO_50"),
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PINCTRL_PIN(51, "GPIO_51"),
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PINCTRL_PIN(52, "GPIO_52"),
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PINCTRL_PIN(53, "GPIO_53"),
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PINCTRL_PIN(54, "GPIO_54"),
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PINCTRL_PIN(55, "GPIO_55"),
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PINCTRL_PIN(56, "GPIO_56"),
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PINCTRL_PIN(57, "GPIO_57"),
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PINCTRL_PIN(58, "GPIO_58"),
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PINCTRL_PIN(59, "GPIO_59"),
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PINCTRL_PIN(60, "GPIO_60"),
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PINCTRL_PIN(61, "GPIO_61"),
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PINCTRL_PIN(62, "GPIO_62"),
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PINCTRL_PIN(63, "GPIO_63"),
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PINCTRL_PIN(64, "GPIO_64"),
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};
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#define DECLARE_MSM_GPIO_PINS(pin) \
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static const unsigned int gpio##pin##_pins[] = { pin }
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DECLARE_MSM_GPIO_PINS(0);
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DECLARE_MSM_GPIO_PINS(1);
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DECLARE_MSM_GPIO_PINS(2);
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DECLARE_MSM_GPIO_PINS(3);
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DECLARE_MSM_GPIO_PINS(4);
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DECLARE_MSM_GPIO_PINS(5);
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DECLARE_MSM_GPIO_PINS(6);
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DECLARE_MSM_GPIO_PINS(7);
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DECLARE_MSM_GPIO_PINS(8);
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DECLARE_MSM_GPIO_PINS(9);
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DECLARE_MSM_GPIO_PINS(10);
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DECLARE_MSM_GPIO_PINS(11);
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DECLARE_MSM_GPIO_PINS(12);
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DECLARE_MSM_GPIO_PINS(13);
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DECLARE_MSM_GPIO_PINS(14);
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DECLARE_MSM_GPIO_PINS(15);
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DECLARE_MSM_GPIO_PINS(16);
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DECLARE_MSM_GPIO_PINS(17);
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DECLARE_MSM_GPIO_PINS(18);
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DECLARE_MSM_GPIO_PINS(19);
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DECLARE_MSM_GPIO_PINS(20);
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DECLARE_MSM_GPIO_PINS(21);
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DECLARE_MSM_GPIO_PINS(22);
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DECLARE_MSM_GPIO_PINS(23);
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DECLARE_MSM_GPIO_PINS(24);
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DECLARE_MSM_GPIO_PINS(25);
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DECLARE_MSM_GPIO_PINS(26);
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DECLARE_MSM_GPIO_PINS(27);
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DECLARE_MSM_GPIO_PINS(28);
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DECLARE_MSM_GPIO_PINS(29);
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DECLARE_MSM_GPIO_PINS(30);
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DECLARE_MSM_GPIO_PINS(31);
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DECLARE_MSM_GPIO_PINS(32);
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DECLARE_MSM_GPIO_PINS(33);
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DECLARE_MSM_GPIO_PINS(34);
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DECLARE_MSM_GPIO_PINS(35);
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DECLARE_MSM_GPIO_PINS(36);
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DECLARE_MSM_GPIO_PINS(37);
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DECLARE_MSM_GPIO_PINS(38);
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DECLARE_MSM_GPIO_PINS(39);
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DECLARE_MSM_GPIO_PINS(40);
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DECLARE_MSM_GPIO_PINS(41);
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DECLARE_MSM_GPIO_PINS(42);
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DECLARE_MSM_GPIO_PINS(43);
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DECLARE_MSM_GPIO_PINS(44);
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DECLARE_MSM_GPIO_PINS(45);
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DECLARE_MSM_GPIO_PINS(46);
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DECLARE_MSM_GPIO_PINS(47);
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DECLARE_MSM_GPIO_PINS(48);
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DECLARE_MSM_GPIO_PINS(49);
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DECLARE_MSM_GPIO_PINS(50);
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DECLARE_MSM_GPIO_PINS(51);
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DECLARE_MSM_GPIO_PINS(52);
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DECLARE_MSM_GPIO_PINS(53);
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DECLARE_MSM_GPIO_PINS(54);
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DECLARE_MSM_GPIO_PINS(55);
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DECLARE_MSM_GPIO_PINS(56);
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DECLARE_MSM_GPIO_PINS(57);
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DECLARE_MSM_GPIO_PINS(58);
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DECLARE_MSM_GPIO_PINS(59);
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DECLARE_MSM_GPIO_PINS(60);
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DECLARE_MSM_GPIO_PINS(61);
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DECLARE_MSM_GPIO_PINS(62);
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DECLARE_MSM_GPIO_PINS(63);
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DECLARE_MSM_GPIO_PINS(64);
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enum ipq9574_functions {
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msm_mux_atest_char,
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msm_mux_atest_char0,
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msm_mux_atest_char1,
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msm_mux_atest_char2,
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msm_mux_atest_char3,
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msm_mux_audio_pdm0,
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msm_mux_audio_pdm1,
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msm_mux_audio_pri,
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msm_mux_audio_sec,
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msm_mux_blsp0_spi,
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msm_mux_blsp0_uart,
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msm_mux_blsp1_i2c,
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msm_mux_blsp1_spi,
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msm_mux_blsp1_uart,
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msm_mux_blsp2_i2c,
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msm_mux_blsp2_spi,
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msm_mux_blsp2_uart,
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msm_mux_blsp3_i2c,
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msm_mux_blsp3_spi,
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msm_mux_blsp3_uart,
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msm_mux_blsp4_i2c,
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msm_mux_blsp4_spi,
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msm_mux_blsp4_uart,
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msm_mux_blsp5_i2c,
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msm_mux_blsp5_uart,
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msm_mux_cri_trng0,
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msm_mux_cri_trng1,
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msm_mux_cri_trng2,
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msm_mux_cri_trng3,
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msm_mux_cxc0,
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msm_mux_cxc1,
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msm_mux_dbg_out,
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msm_mux_dwc_ddrphy,
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msm_mux_gcc_plltest,
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msm_mux_gcc_tlmm,
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msm_mux_gpio,
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msm_mux_mac,
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msm_mux_mdc,
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msm_mux_mdio,
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msm_mux_pcie0_clk,
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msm_mux_pcie0_wake,
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msm_mux_pcie1_clk,
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msm_mux_pcie1_wake,
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msm_mux_pcie2_clk,
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msm_mux_pcie2_wake,
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msm_mux_pcie3_clk,
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msm_mux_pcie3_wake,
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msm_mux_prng_rosc0,
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msm_mux_prng_rosc1,
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msm_mux_prng_rosc2,
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msm_mux_prng_rosc3,
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msm_mux_pta,
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msm_mux_pwm,
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msm_mux_qdss_cti_trig_in_a0,
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msm_mux_qdss_cti_trig_in_a1,
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msm_mux_qdss_cti_trig_in_b0,
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msm_mux_qdss_cti_trig_in_b1,
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msm_mux_qdss_cti_trig_out_a0,
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msm_mux_qdss_cti_trig_out_a1,
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msm_mux_qdss_cti_trig_out_b0,
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msm_mux_qdss_cti_trig_out_b1,
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msm_mux_qdss_traceclk_a,
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msm_mux_qdss_traceclk_b,
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msm_mux_qdss_tracectl_a,
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msm_mux_qdss_tracectl_b,
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msm_mux_qdss_tracedata_a,
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msm_mux_qdss_tracedata_b,
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msm_mux_qspi_data,
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msm_mux_qspi_clk,
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msm_mux_qspi_cs,
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msm_mux_rx0,
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msm_mux_rx1,
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msm_mux_sdc_data,
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msm_mux_sdc_clk,
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msm_mux_sdc_cmd,
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msm_mux_sdc_rclk,
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msm_mux_tsens_max,
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msm_mux_wci20,
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msm_mux_wci21,
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msm_mux_wsa_swrm,
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msm_mux__,
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};
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static const char * const gpio_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
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"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
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"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
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"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
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"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
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"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
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"gpio64",
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};
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static const char * const sdc_data_groups[] = {
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"gpio0",
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"gpio1",
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"gpio2",
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"gpio3",
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"gpio6",
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"gpio7",
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"gpio8",
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"gpio9",
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};
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static const char * const qspi_data_groups[] = {
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"gpio0",
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"gpio1",
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"gpio2",
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"gpio3",
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};
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static const char * const qdss_traceclk_b_groups[] = {
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"gpio0",
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};
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static const char * const qdss_tracectl_b_groups[] = {
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"gpio1",
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};
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static const char * const qdss_tracedata_b_groups[] = {
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"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
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"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
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"gpio17",
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};
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static const char * const sdc_cmd_groups[] = {
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"gpio4",
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};
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static const char * const qspi_cs_groups[] = {
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"gpio4",
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};
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static const char * const sdc_clk_groups[] = {
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"gpio5",
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};
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static const char * const qspi_clk_groups[] = {
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"gpio5",
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};
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static const char * const sdc_rclk_groups[] = {
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"gpio10",
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};
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static const char * const blsp0_spi_groups[] = {
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"gpio11", "gpio12", "gpio13", "gpio14",
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};
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static const char * const blsp0_uart_groups[] = {
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"gpio11", "gpio12", "gpio13", "gpio14",
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};
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static const char * const blsp3_spi_groups[] = {
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
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};
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static const char * const blsp3_i2c_groups[] = {
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"gpio15", "gpio16",
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};
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static const char * const blsp3_uart_groups[] = {
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"gpio15", "gpio16", "gpio17", "gpio18",
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};
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static const char * const dbg_out_groups[] = {
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"gpio17",
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};
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static const char * const cri_trng0_groups[] = {
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"gpio20", "gpio38",
|
||||
};
|
||||
|
||||
static const char * const cri_trng1_groups[] = {
|
||||
"gpio21", "gpio34",
|
||||
};
|
||||
|
||||
static const char * const pcie0_clk_groups[] = {
|
||||
"gpio22",
|
||||
};
|
||||
|
||||
static const char * const pta_groups[] = {
|
||||
"gpio22", "gpio23", "gpio24", "gpio54", "gpio55", "gpio56", "gpio61",
|
||||
"gpio62", "gpio63",
|
||||
};
|
||||
|
||||
static const char * const wci21_groups[] = {
|
||||
"gpio23", "gpio24",
|
||||
};
|
||||
|
||||
static const char * const cxc0_groups[] = {
|
||||
"gpio23", "gpio24",
|
||||
};
|
||||
|
||||
static const char * const pcie0_wake_groups[] = {
|
||||
"gpio24",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_b0_groups[] = {
|
||||
"gpio24",
|
||||
};
|
||||
|
||||
static const char * const pcie1_clk_groups[] = {
|
||||
"gpio25",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_b0_groups[] = {
|
||||
"gpio25",
|
||||
};
|
||||
|
||||
static const char * const atest_char0_groups[] = {
|
||||
"gpio26",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_b1_groups[] = {
|
||||
"gpio26",
|
||||
};
|
||||
|
||||
static const char * const pcie1_wake_groups[] = {
|
||||
"gpio27",
|
||||
};
|
||||
|
||||
static const char * const atest_char1_groups[] = {
|
||||
"gpio27",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_b1_groups[] = {
|
||||
"gpio27",
|
||||
};
|
||||
|
||||
static const char * const pcie2_clk_groups[] = {
|
||||
"gpio28",
|
||||
};
|
||||
|
||||
static const char * const atest_char2_groups[] = {
|
||||
"gpio28",
|
||||
};
|
||||
|
||||
static const char * const atest_char3_groups[] = {
|
||||
"gpio29",
|
||||
};
|
||||
|
||||
static const char * const pcie2_wake_groups[] = {
|
||||
"gpio30",
|
||||
};
|
||||
|
||||
static const char * const pwm_groups[] = {
|
||||
"gpio30", "gpio31", "gpio32", "gpio33", "gpio44", "gpio45", "gpio46",
|
||||
"gpio47", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55",
|
||||
"gpio56", "gpio57", "gpio58", "gpio59", "gpio60",
|
||||
};
|
||||
|
||||
static const char * const atest_char_groups[] = {
|
||||
"gpio30",
|
||||
};
|
||||
|
||||
static const char * const pcie3_clk_groups[] = {
|
||||
"gpio31",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_a1_groups[] = {
|
||||
"gpio31",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_a1_groups[] = {
|
||||
"gpio32",
|
||||
};
|
||||
|
||||
static const char * const pcie3_wake_groups[] = {
|
||||
"gpio33",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_in_a0_groups[] = {
|
||||
"gpio33",
|
||||
};
|
||||
|
||||
static const char * const blsp2_uart_groups[] = {
|
||||
"gpio34", "gpio35",
|
||||
};
|
||||
|
||||
static const char * const blsp2_i2c_groups[] = {
|
||||
"gpio34", "gpio35",
|
||||
};
|
||||
|
||||
static const char * const blsp2_spi_groups[] = {
|
||||
"gpio34", "gpio35", "gpio36", "gpio37",
|
||||
};
|
||||
|
||||
static const char * const blsp1_uart_groups[] = {
|
||||
"gpio34", "gpio35", "gpio36", "gpio37",
|
||||
};
|
||||
|
||||
static const char * const qdss_cti_trig_out_a0_groups[] = {
|
||||
"gpio34",
|
||||
};
|
||||
|
||||
static const char * const cri_trng2_groups[] = {
|
||||
"gpio35",
|
||||
};
|
||||
|
||||
static const char * const blsp1_i2c_groups[] = {
|
||||
"gpio36", "gpio37",
|
||||
};
|
||||
|
||||
static const char * const cri_trng3_groups[] = {
|
||||
"gpio36",
|
||||
};
|
||||
|
||||
static const char * const dwc_ddrphy_groups[] = {
|
||||
"gpio37",
|
||||
};
|
||||
|
||||
static const char * const mdc_groups[] = {
|
||||
"gpio38",
|
||||
};
|
||||
|
||||
static const char * const mdio_groups[] = {
|
||||
"gpio39",
|
||||
};
|
||||
|
||||
static const char * const audio_pri_groups[] = {
|
||||
"gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61",
|
||||
};
|
||||
|
||||
static const char * const audio_pdm0_groups[] = {
|
||||
"gpio40", "gpio41", "gpio42", "gpio43",
|
||||
};
|
||||
|
||||
static const char * const qdss_traceclk_a_groups[] = {
|
||||
"gpio43",
|
||||
};
|
||||
|
||||
static const char * const audio_sec_groups[] = {
|
||||
"gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62",
|
||||
};
|
||||
|
||||
static const char * const wsa_swrm_groups[] = {
|
||||
"gpio44", "gpio45",
|
||||
};
|
||||
|
||||
static const char * const qdss_tracectl_a_groups[] = {
|
||||
"gpio44",
|
||||
};
|
||||
|
||||
static const char * const qdss_tracedata_a_groups[] = {
|
||||
"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
|
||||
"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
|
||||
"gpio59", "gpio60",
|
||||
};
|
||||
|
||||
static const char * const rx1_groups[] = {
|
||||
"gpio46",
|
||||
};
|
||||
|
||||
static const char * const mac_groups[] = {
|
||||
"gpio46", "gpio47", "gpio57", "gpio58",
|
||||
};
|
||||
|
||||
static const char * const blsp5_i2c_groups[] = {
|
||||
"gpio48", "gpio49",
|
||||
};
|
||||
|
||||
static const char * const blsp5_uart_groups[] = {
|
||||
"gpio48", "gpio49",
|
||||
};
|
||||
|
||||
static const char * const blsp4_uart_groups[] = {
|
||||
"gpio50", "gpio51", "gpio52", "gpio53",
|
||||
};
|
||||
|
||||
static const char * const blsp4_i2c_groups[] = {
|
||||
"gpio50", "gpio51",
|
||||
};
|
||||
|
||||
static const char * const blsp4_spi_groups[] = {
|
||||
"gpio50", "gpio51", "gpio52", "gpio53",
|
||||
};
|
||||
|
||||
static const char * const wci20_groups[] = {
|
||||
"gpio57", "gpio58",
|
||||
};
|
||||
|
||||
static const char * const cxc1_groups[] = {
|
||||
"gpio57", "gpio58",
|
||||
};
|
||||
|
||||
static const char * const rx0_groups[] = {
|
||||
"gpio59",
|
||||
};
|
||||
|
||||
static const char * const prng_rosc0_groups[] = {
|
||||
"gpio60",
|
||||
};
|
||||
|
||||
static const char * const gcc_plltest_groups[] = {
|
||||
"gpio60", "gpio62",
|
||||
};
|
||||
|
||||
static const char * const blsp1_spi_groups[] = {
|
||||
"gpio61", "gpio62", "gpio63", "gpio64",
|
||||
};
|
||||
|
||||
static const char * const audio_pdm1_groups[] = {
|
||||
"gpio61", "gpio62", "gpio63", "gpio64",
|
||||
};
|
||||
|
||||
static const char * const prng_rosc1_groups[] = {
|
||||
"gpio61",
|
||||
};
|
||||
|
||||
static const char * const gcc_tlmm_groups[] = {
|
||||
"gpio61",
|
||||
};
|
||||
|
||||
static const char * const prng_rosc2_groups[] = {
|
||||
"gpio62",
|
||||
};
|
||||
|
||||
static const char * const prng_rosc3_groups[] = {
|
||||
"gpio63",
|
||||
};
|
||||
|
||||
static const char * const tsens_max_groups[] = {
|
||||
"gpio64",
|
||||
};
|
||||
|
||||
static const struct msm_function ipq9574_functions[] = {
|
||||
FUNCTION(atest_char),
|
||||
FUNCTION(atest_char0),
|
||||
FUNCTION(atest_char1),
|
||||
FUNCTION(atest_char2),
|
||||
FUNCTION(atest_char3),
|
||||
FUNCTION(audio_pdm0),
|
||||
FUNCTION(audio_pdm1),
|
||||
FUNCTION(audio_pri),
|
||||
FUNCTION(audio_sec),
|
||||
FUNCTION(blsp0_spi),
|
||||
FUNCTION(blsp0_uart),
|
||||
FUNCTION(blsp1_i2c),
|
||||
FUNCTION(blsp1_spi),
|
||||
FUNCTION(blsp1_uart),
|
||||
FUNCTION(blsp2_i2c),
|
||||
FUNCTION(blsp2_spi),
|
||||
FUNCTION(blsp2_uart),
|
||||
FUNCTION(blsp3_i2c),
|
||||
FUNCTION(blsp3_spi),
|
||||
FUNCTION(blsp3_uart),
|
||||
FUNCTION(blsp4_i2c),
|
||||
FUNCTION(blsp4_spi),
|
||||
FUNCTION(blsp4_uart),
|
||||
FUNCTION(blsp5_i2c),
|
||||
FUNCTION(blsp5_uart),
|
||||
FUNCTION(cri_trng0),
|
||||
FUNCTION(cri_trng1),
|
||||
FUNCTION(cri_trng2),
|
||||
FUNCTION(cri_trng3),
|
||||
FUNCTION(cxc0),
|
||||
FUNCTION(cxc1),
|
||||
FUNCTION(dbg_out),
|
||||
FUNCTION(dwc_ddrphy),
|
||||
FUNCTION(gcc_plltest),
|
||||
FUNCTION(gcc_tlmm),
|
||||
FUNCTION(gpio),
|
||||
FUNCTION(mac),
|
||||
FUNCTION(mdc),
|
||||
FUNCTION(mdio),
|
||||
FUNCTION(pcie0_clk),
|
||||
FUNCTION(pcie0_wake),
|
||||
FUNCTION(pcie1_clk),
|
||||
FUNCTION(pcie1_wake),
|
||||
FUNCTION(pcie2_clk),
|
||||
FUNCTION(pcie2_wake),
|
||||
FUNCTION(pcie3_clk),
|
||||
FUNCTION(pcie3_wake),
|
||||
FUNCTION(prng_rosc0),
|
||||
FUNCTION(prng_rosc1),
|
||||
FUNCTION(prng_rosc2),
|
||||
FUNCTION(prng_rosc3),
|
||||
FUNCTION(pta),
|
||||
FUNCTION(pwm),
|
||||
FUNCTION(qdss_cti_trig_in_a0),
|
||||
FUNCTION(qdss_cti_trig_in_a1),
|
||||
FUNCTION(qdss_cti_trig_in_b0),
|
||||
FUNCTION(qdss_cti_trig_in_b1),
|
||||
FUNCTION(qdss_cti_trig_out_a0),
|
||||
FUNCTION(qdss_cti_trig_out_a1),
|
||||
FUNCTION(qdss_cti_trig_out_b0),
|
||||
FUNCTION(qdss_cti_trig_out_b1),
|
||||
FUNCTION(qdss_traceclk_a),
|
||||
FUNCTION(qdss_traceclk_b),
|
||||
FUNCTION(qdss_tracectl_a),
|
||||
FUNCTION(qdss_tracectl_b),
|
||||
FUNCTION(qdss_tracedata_a),
|
||||
FUNCTION(qdss_tracedata_b),
|
||||
FUNCTION(qspi_data),
|
||||
FUNCTION(qspi_clk),
|
||||
FUNCTION(qspi_cs),
|
||||
FUNCTION(rx0),
|
||||
FUNCTION(rx1),
|
||||
FUNCTION(sdc_data),
|
||||
FUNCTION(sdc_clk),
|
||||
FUNCTION(sdc_cmd),
|
||||
FUNCTION(sdc_rclk),
|
||||
FUNCTION(tsens_max),
|
||||
FUNCTION(wci20),
|
||||
FUNCTION(wci21),
|
||||
FUNCTION(wsa_swrm),
|
||||
};
|
||||
|
||||
static const struct msm_pingroup ipq9574_groups[] = {
|
||||
PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),
|
||||
PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),
|
||||
PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),
|
||||
PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),
|
||||
PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _),
|
||||
PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _),
|
||||
PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _, _, _, _),
|
||||
PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),
|
||||
PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),
|
||||
PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),
|
||||
PINGROUP(22, pcie0_clk, _, pta, _, _, _, _, _, _),
|
||||
PINGROUP(23, _, pta, wci21, cxc0, _, _, _, _, _),
|
||||
PINGROUP(24, pcie0_wake, _, pta, wci21, cxc0, _, qdss_cti_trig_out_b0, _, _),
|
||||
PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _, _),
|
||||
PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _, _),
|
||||
PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _, _, _, _),
|
||||
PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),
|
||||
PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(30, pcie2_wake, pwm, atest_char, _, _, _, _, _, _),
|
||||
PINGROUP(31, pcie3_clk, pwm, _, qdss_cti_trig_in_a1, _, _, _, _, _),
|
||||
PINGROUP(32, pwm, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),
|
||||
PINGROUP(33, pcie3_wake, pwm, _, qdss_cti_trig_in_a0, _, _, _, _, _),
|
||||
PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng1, qdss_cti_trig_out_a0, _, _),
|
||||
PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng2, _, _, _),
|
||||
PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _, _, _),
|
||||
PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _, _, _),
|
||||
PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
|
||||
PINGROUP(39, mdio, _, _, _, _, _, _, _, _),
|
||||
PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
|
||||
PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
|
||||
PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
|
||||
PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _, _, _),
|
||||
PINGROUP(44, pwm, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _, _, _),
|
||||
PINGROUP(45, pwm, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(46, pwm, audio_sec, rx1, mac, _, qdss_tracedata_a, _, _, _),
|
||||
PINGROUP(47, pwm, audio_sec, mac, _, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(52, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(53, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _),
|
||||
PINGROUP(54, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),
|
||||
PINGROUP(55, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),
|
||||
PINGROUP(56, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),
|
||||
PINGROUP(57, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(58, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _),
|
||||
PINGROUP(59, rx0, pwm, qdss_tracedata_a, _, _, _, _, _, _),
|
||||
PINGROUP(60, pwm, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _, _, _, _),
|
||||
PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta, prng_rosc1, gcc_tlmm, _, _),
|
||||
PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta, prng_rosc2, gcc_plltest, _, _),
|
||||
PINGROUP(63, blsp1_spi, audio_pdm1, pta, prng_rosc3, _, _, _, _, _),
|
||||
PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),
|
||||
};
|
||||
|
||||
/* Reserving GPIO59 for controlling the QFPROM LDO regulator */
|
||||
static const int ipq9574_reserved_gpios[] = {
|
||||
59, -1
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
|
||||
.pins = ipq9574_pins,
|
||||
.npins = ARRAY_SIZE(ipq9574_pins),
|
||||
.functions = ipq9574_functions,
|
||||
.nfunctions = ARRAY_SIZE(ipq9574_functions),
|
||||
.groups = ipq9574_groups,
|
||||
.ngroups = ARRAY_SIZE(ipq9574_groups),
|
||||
.reserved_gpios = ipq9574_reserved_gpios,
|
||||
.ngpios = 65,
|
||||
};
|
||||
|
||||
static int ipq9574_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
|
||||
}
|
||||
|
||||
static const struct of_device_id ipq9574_pinctrl_of_match[] = {
|
||||
{ .compatible = "qcom,ipq9574-tlmm", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver ipq9574_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "ipq9574-tlmm",
|
||||
.of_match_table = ipq9574_pinctrl_of_match,
|
||||
},
|
||||
.probe = ipq9574_pinctrl_probe,
|
||||
.remove = msm_pinctrl_remove,
|
||||
};
|
||||
|
||||
static int __init ipq9574_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&ipq9574_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(ipq9574_pinctrl_init);
|
||||
|
||||
static void __exit ipq9574_pinctrl_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&ipq9574_pinctrl_driver);
|
||||
}
|
||||
module_exit(ipq9574_pinctrl_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user