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iwlagn: Clarify FH_TX interrupt
Add/clarify comments and debug messages for interrupt used only for uCode load Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1033,11 +1033,12 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
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handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
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}
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/* This "Tx" DMA channel is used only for loading uCode */
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if (inta & CSR_INT_BIT_FH_TX) {
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IWL_DEBUG_ISR(priv, "Tx interrupt\n");
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IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
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priv->isr_stats.tx++;
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handled |= CSR_INT_BIT_FH_TX;
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/* FH finished to write, send event */
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/* Wake up uCode load routine, now that load is complete */
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priv->ucode_write_complete = 1;
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wake_up_interruptible(&priv->wait_command_queue);
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}
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@ -1234,12 +1235,13 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
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iwl_leds_background(priv);
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}
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/* This "Tx" DMA channel is used only for loading uCode */
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if (inta & CSR_INT_BIT_FH_TX) {
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iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
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IWL_DEBUG_ISR(priv, "Tx interrupt\n");
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IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
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priv->isr_stats.tx++;
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handled |= CSR_INT_BIT_FH_TX;
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/* FH finished to write, send event */
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/* Wake up uCode load routine, now that load is complete */
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priv->ucode_write_complete = 1;
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wake_up_interruptible(&priv->wait_command_queue);
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}
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