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net/mlx5: mlx5_ifc update for accessing ppcnt register of plane ports
This patch adds new fields to support multi-plane and the extend port counters group. Actual support will be added in the next patch. Signed-off-by: Mark Zhang <markzhang@nvidia.com> Link: https://lore.kernel.org/r/70221cdd79aad0e21cbf385d9567e3ebffbc5137.1718553901.git.leon@kernel.org Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
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@ -2651,6 +2651,46 @@ struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
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u8 port_xmit_wait[0x20];
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};
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struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
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u8 reserved_at_0[0x300];
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u8 port_xmit_data_high[0x20];
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u8 port_xmit_data_low[0x20];
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u8 port_rcv_data_high[0x20];
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u8 port_rcv_data_low[0x20];
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u8 port_xmit_pkts_high[0x20];
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u8 port_xmit_pkts_low[0x20];
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u8 port_rcv_pkts_high[0x20];
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u8 port_rcv_pkts_low[0x20];
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u8 reserved_at_400[0x80];
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u8 port_unicast_xmit_pkts_high[0x20];
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u8 port_unicast_xmit_pkts_low[0x20];
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u8 port_multicast_xmit_pkts_high[0x20];
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u8 port_multicast_xmit_pkts_low[0x20];
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u8 port_unicast_rcv_pkts_high[0x20];
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u8 port_unicast_rcv_pkts_low[0x20];
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u8 port_multicast_rcv_pkts_high[0x20];
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u8 port_multicast_rcv_pkts_low[0x20];
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u8 reserved_at_580[0x240];
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};
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struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
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u8 transmit_queue_high[0x20];
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@ -4543,6 +4583,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
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struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
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struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
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struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
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struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
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struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
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struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
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u8 reserved_at_0[0x7c0];
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@ -9851,8 +9892,10 @@ struct mlx5_ifc_ppcnt_reg_bits {
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u8 grp[0x6];
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u8 clr[0x1];
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u8 reserved_at_21[0x1c];
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u8 prio_tc[0x3];
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u8 reserved_at_21[0x13];
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u8 plane_ind[0x4];
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u8 reserved_at_38[0x3];
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u8 prio_tc[0x5];
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union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
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};
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