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aacraid: Enable 64bit write to controller register
If writeq() not supported, then do atomic two 32bit write Reviewed-by: Tomas Henzl <thenzl@redhat.com> Reviewed-by: Murthy Bhat <Murthy.Bhat@pmcs.com> Reviewed-by: Karthikeya Sunkesula <Karthikeya.Sunkesula@pmcs.com> Signed-off-by: Mahesh Rajashekhara <Mahesh.Rajashekhara@pmcs.com> Signed-off-by: James Bottomley <JBottomley@Odin.com>
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@ -844,6 +844,10 @@ struct src_registers {
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&((AEP)->regs.src.bar0->CSR))
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#define src_writel(AEP, CSR, value) writel(value, \
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&((AEP)->regs.src.bar0->CSR))
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#if defined(writeq)
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#define src_writeq(AEP, CSR, value) writeq(value, \
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&((AEP)->regs.src.bar0->CSR))
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#endif
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#define SRC_ODR_SHIFT 12
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#define SRC_IDR_SHIFT 9
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@ -1163,6 +1167,11 @@ struct aac_dev
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struct fsa_dev_info *fsa_dev;
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struct task_struct *thread;
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int cardtype;
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/*
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*This lock will protect the two 32-bit
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*writes to the Inbound Queue
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*/
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spinlock_t iq_lock;
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/*
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* The following is the device specific extension.
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@ -424,6 +424,7 @@ struct aac_dev *aac_init_adapter(struct aac_dev *dev)
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dev->management_fib_count = 0;
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spin_lock_init(&dev->manage_lock);
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spin_lock_init(&dev->sync_lock);
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spin_lock_init(&dev->iq_lock);
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dev->max_fib_size = sizeof(struct hw_fib);
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dev->sg_tablesize = host->sg_tablesize = (dev->max_fib_size
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- sizeof(struct aac_fibhdr)
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@ -447,6 +447,10 @@ static int aac_src_deliver_message(struct fib *fib)
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u32 fibsize;
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dma_addr_t address;
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struct aac_fib_xporthdr *pFibX;
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#if !defined(writeq)
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unsigned long flags;
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#endif
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u16 hdr_size = le16_to_cpu(fib->hw_fib_va->header.Size);
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atomic_inc(&q->numpending);
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@ -511,10 +515,14 @@ static int aac_src_deliver_message(struct fib *fib)
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return -EINVAL;
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address |= fibsize;
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}
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#if defined(writeq)
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src_writeq(dev, MUnit.IQ_L, (u64)address);
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#else
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spin_lock_irqsave(&fib->dev->iq_lock, flags);
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src_writel(dev, MUnit.IQ_H, upper_32_bits(address) & 0xffffffff);
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src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
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spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
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#endif
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return 0;
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}
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