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x86, mce: make mce_disabled boolean
The mce_disabled on 32bit is a tristate variable [1,0,-1], while 64bit version is boolean [0,1]. This patch makes mce_disabled always boolean, and use mce_p5_enabled to indicate the third state instead. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -107,6 +107,7 @@ struct mce_log {
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#include <asm/atomic.h>
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#include <asm/atomic.h>
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extern int mce_disabled;
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extern int mce_disabled;
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extern int mce_p5_enabled;
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#ifdef CONFIG_X86_OLD_MCE
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#ifdef CONFIG_X86_OLD_MCE
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void amd_mcheck_init(struct cpuinfo_x86 *c);
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void amd_mcheck_init(struct cpuinfo_x86 *c);
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@ -117,14 +118,11 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
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#ifdef CONFIG_X86_ANCIENT_MCE
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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extern int mce_p5_enable;
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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static inline int mce_p5_enabled(void) { return mce_p5_enable; }
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static inline void enable_p5_mce(void) { mce_p5_enable = 1; }
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#else
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline int mce_p5_enabled(void) { return 0; }
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static inline void enable_p5_mce(void) {}
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static inline void enable_p5_mce(void) { }
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#endif
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#endif
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/* Call the installed machine check handler for this CPU setup. */
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/* Call the installed machine check handler for this CPU setup. */
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@ -1286,8 +1286,7 @@ static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
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return;
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return;
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switch (c->x86_vendor) {
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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case X86_VENDOR_INTEL:
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if (mce_p5_enabled())
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intel_p5_mcheck_init(c);
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intel_p5_mcheck_init(c);
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break;
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break;
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case X86_VENDOR_CENTAUR:
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case X86_VENDOR_CENTAUR:
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winchip_mcheck_init(c);
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winchip_mcheck_init(c);
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@ -2002,7 +2001,7 @@ EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
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/* This has to be run for each processor */
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/* This has to be run for each processor */
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void mcheck_init(struct cpuinfo_x86 *c)
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void mcheck_init(struct cpuinfo_x86 *c)
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{
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{
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if (mce_disabled == 1)
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if (mce_disabled)
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return;
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return;
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switch (c->x86_vendor) {
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switch (c->x86_vendor) {
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@ -2032,10 +2031,9 @@ void mcheck_init(struct cpuinfo_x86 *c)
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static int __init mcheck_enable(char *str)
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static int __init mcheck_enable(char *str)
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{
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{
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mce_disabled = -1;
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mce_p5_enabled = 1;
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return 1;
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return 1;
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}
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}
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__setup("mce", mcheck_enable);
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__setup("mce", mcheck_enable);
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#endif /* CONFIG_X86_OLD_MCE */
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#endif /* CONFIG_X86_OLD_MCE */
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@ -14,7 +14,7 @@
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#include <asm/msr.h>
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#include <asm/msr.h>
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/* By default disabled */
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/* By default disabled */
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int mce_p5_enable;
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int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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/* Machine check handler for Pentium class Intel CPUs: */
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static void pentium_machine_check(struct pt_regs *regs, long error_code)
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static void pentium_machine_check(struct pt_regs *regs, long error_code)
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@ -42,16 +42,14 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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{
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u32 l, h;
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u32 l, h;
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/* Default P5 to off as its often misconnected: */
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if (!mce_p5_enabled)
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return;
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/* Check for MCE support: */
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/* Check for MCE support: */
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if (!cpu_has(c, X86_FEATURE_MCE))
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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return;
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#ifdef CONFIG_X86_OLD_MCE
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/* Default P5 to off as its often misconnected: */
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if (mce_disabled != -1)
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return;
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#endif
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machine_check_vector = pentium_machine_check;
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machine_check_vector = pentium_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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wmb();
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