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pmic wrapper:

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- add mt8516 bindings
 - add mt8516 driver support
 - fix clang warning
 -----BEGIN PGP SIGNATURE-----
 
 iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAly/OBUXHG1hdHRoaWFz
 LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Ng4g//UBksTwzGlrgqlSS+GeEgIll2
 a3srqbjePGeAFT4P5IVnp68ubOntzoOu4tB+tVvu2HnCBcdTkR2F/UKrCXzOHSYV
 QsdH/u9KnMxZw6kOUtL5CgfF/y6gjz0ZKBY6i3wxgnb1bUuXbAWk0NJ/yVaJF7M+
 J7lRr00AvN6RROmLT2iD84+5Q809vy96iPyashBO40iCSW5qipg1NIBED+UelGgL
 WzGuEoWd8c4dN80T5Lmk/A3rQGU6JVIV2MJ/iLWDBgVBzs8CMV83Tnx1pUQx5+jq
 EgahvygjQOXjJ6ySuSg7bhgJktpnaHVK+fL3xB1Zr6xhstWNTpw/RG6BvLMZ524Y
 0FtyNaHgiD64pf32MBdrlKBtGhBhU2oVfFIZEmjg7JMJ/BpOLJ6v5z+WX3kmEQr5
 GhmGIu7i+K4izER2E24lCLs7u8sIA2oiurjs3tS9XoFN70ahFiKodx1LCKFtN0yH
 wil6b6GNc/SbKNXTHo0Sw+a2aeDs6njcd2A1eMPBjWcF6XfNFaOuaGTsIcR64wHP
 sxVv39dg0nC4aGgzOhNXD90xpOoJU2eoylnot3k8p1fu6L84CO4OaGYZ4jGUYCr0
 N9iP6P3LLPFMUF7Pd6aJEuoox53sxlMdM1gF/YkR/Fd85e8YDaYFuTS228qvHevm
 WS/pH7Kk76q3Ao4s2wU=
 =L0TN
 -----END PGP SIGNATURE-----

Merge tag 'v5.1-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

pmic wrapper:
- add mt8516 bindings
- add mt8516 driver support
- fix clang warning

* tag 'v5.1-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: pwrap: Zero initialize rdata in pwrap_init_cipher
  soc: mediatek: pwrap: add support for MT8516 pwrap
  soc: mediatek: pwrap: add missing check on rstc
  dt-bindings: pwrap: mediatek: add pwrap support for MT8516

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-29 09:52:30 -07:00
commit c687702b5f
2 changed files with 110 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@ -25,6 +25,7 @@ Required properties in pwrap device node.
"mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: Must include the following entries:
"pwrap": Main registers base

111
drivers/soc/mediatek/mtk-pmic-wrap.c
View File

@ -381,6 +381,10 @@ enum pwrap_regs {
PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
PWRAP_GPSINF_0_STA,
PWRAP_GPSINF_1_STA,
/* MT8516 only regs */
PWRAP_OP_TYPE,
PWRAP_MSB_FIRST,
};
static int mt2701_regs[] = {
@ -852,6 +856,91 @@ static int mt8183_regs[] = {
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
static int mt8516_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_RDDMY] = 0x10,
[PWRAP_SI_CK_CON] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1c,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_STAUPD_GRPEN] = 0x2c,
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
[PWRAP_STAUPD_STA] = 0x44,
[PWRAP_WRAP_STA] = 0x48,
[PWRAP_HARB_INIT] = 0x4c,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_HARB_STA0] = 0x58,
[PWRAP_HARB_STA1] = 0x5c,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_MAN_RDATA] = 0x68,
[PWRAP_MAN_VLDCLR] = 0x6c,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_INIT_DONE0] = 0x74,
[PWRAP_WACS0_CMD] = 0x78,
[PWRAP_WACS0_RDATA] = 0x7c,
[PWRAP_WACS0_VLDCLR] = 0x80,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_INIT_DONE1] = 0x88,
[PWRAP_WACS1_CMD] = 0x8c,
[PWRAP_WACS1_RDATA] = 0x90,
[PWRAP_WACS1_VLDCLR] = 0x94,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9c,
[PWRAP_WACS2_CMD] = 0xa0,
[PWRAP_WACS2_RDATA] = 0xa4,
[PWRAP_WACS2_VLDCLR] = 0xa8,
[PWRAP_INT_EN] = 0xac,
[PWRAP_INT_FLG_RAW] = 0xb0,
[PWRAP_INT_FLG] = 0xb4,
[PWRAP_INT_CLR] = 0xb8,
[PWRAP_SIG_ADR] = 0xbc,
[PWRAP_SIG_MODE] = 0xc0,
[PWRAP_SIG_VALUE] = 0xc4,
[PWRAP_SIG_ERRVAL] = 0xc8,
[PWRAP_CRC_EN] = 0xcc,
[PWRAP_TIMER_EN] = 0xd0,
[PWRAP_TIMER_STA] = 0xd4,
[PWRAP_WDT_UNIT] = 0xd8,
[PWRAP_WDT_SRC_EN] = 0xdc,
[PWRAP_WDT_FLG] = 0xe0,
[PWRAP_DEBUG_INT_SEL] = 0xe4,
[PWRAP_DVFS_ADR0] = 0xe8,
[PWRAP_DVFS_WDATA0] = 0xec,
[PWRAP_DVFS_ADR1] = 0xf0,
[PWRAP_DVFS_WDATA1] = 0xf4,
[PWRAP_DVFS_ADR2] = 0xf8,
[PWRAP_DVFS_WDATA2] = 0xfc,
[PWRAP_DVFS_ADR3] = 0x100,
[PWRAP_DVFS_WDATA3] = 0x104,
[PWRAP_DVFS_ADR4] = 0x108,
[PWRAP_DVFS_WDATA4] = 0x10c,
[PWRAP_DVFS_ADR5] = 0x110,
[PWRAP_DVFS_WDATA5] = 0x114,
[PWRAP_DVFS_ADR6] = 0x118,
[PWRAP_DVFS_WDATA6] = 0x11c,
[PWRAP_DVFS_ADR7] = 0x120,
[PWRAP_DVFS_WDATA7] = 0x124,
[PWRAP_SPMINF_STA] = 0x128,
[PWRAP_CIPHER_KEY_SEL] = 0x12c,
[PWRAP_CIPHER_IV_SEL] = 0x130,
[PWRAP_CIPHER_EN] = 0x134,
[PWRAP_CIPHER_RDY] = 0x138,
[PWRAP_CIPHER_MODE] = 0x13c,
[PWRAP_CIPHER_SWRST] = 0x140,
[PWRAP_DCM_EN] = 0x144,
[PWRAP_DCM_DBC_PRD] = 0x148,
[PWRAP_SW_RST] = 0x168,
[PWRAP_OP_TYPE] = 0x16c,
[PWRAP_MSB_FIRST] = 0x170,
};
enum pmic_type {
PMIC_MT6323,
PMIC_MT6351,
@ -869,6 +958,7 @@ enum pwrap_type {
PWRAP_MT8135,
PWRAP_MT8173,
PWRAP_MT8183,
PWRAP_MT8516,
};
struct pmic_wrapper;
@ -1281,7 +1371,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
static int pwrap_init_cipher(struct pmic_wrapper *wrp)
{
int ret;
u32 rdata;
u32 rdata = 0;
pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
@ -1297,6 +1387,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
case PWRAP_MT6765:
case PWRAP_MT6797:
case PWRAP_MT8173:
case PWRAP_MT8516:
pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
break;
case PWRAP_MT7622:
@ -1478,7 +1569,8 @@ static int pwrap_init(struct pmic_wrapper *wrp)
{
int ret;
reset_control_reset(wrp->rstc);
if (wrp->rstc)
reset_control_reset(wrp->rstc);
if (wrp->rstc_bridge)
reset_control_reset(wrp->rstc_bridge);
@ -1764,6 +1856,18 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
.init_soc_specific = pwrap_mt8183_init_soc_specific,
};
static struct pmic_wrapper_type pwrap_mt8516 = {
.regs = mt8516_regs,
.type = PWRAP_MT8516,
.arb_en_all = 0xff,
.int_en_all = ~(u32)(BIT(31) | BIT(2)),
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_DCM,
.init_reg_clock = pwrap_mt2701_init_reg_clock,
.init_soc_specific = NULL,
};
static const struct of_device_id of_pwrap_match_tbl[] = {
{
.compatible = "mediatek,mt2701-pwrap",
@ -1786,6 +1890,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
}, {
.compatible = "mediatek,mt8183-pwrap",
.data = &pwrap_mt8183,
}, {
.compatible = "mediatek,mt8516-pwrap",
.data = &pwrap_mt8516,
}, {
/* sentinel */
}