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dt-bindings: mmc: Convert mtk-sd to json-schema
Convert the mtk-sd binding to DT schema format using json-schema. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201014030846.12428-2-wenbin.mei@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Wenbin Mei
Ulf Hansson
parent
e10f480902
commit
c626695ecd
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* MTK MMC controller
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The MTK MSDC can act as a MMC controller
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to support MMC, SD, and SDIO types of memory cards.
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This file documents differences between the core properties in mmc.txt
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and the properties used by the msdc driver.
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Required properties:
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- compatible: value should be either of the following.
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"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
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"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
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"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
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"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
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"mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
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"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
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"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
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"mediatek,mt7622-mmc": for MT7622 SoC
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"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
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"mediatek,mt7620-mmc", for MT7621 SoC (and others)
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- reg: physical base address of the controller and length
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- interrupts: Should contain MSDC interrupt number
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- clocks: Should contain phandle for the clock feeding the MMC controller
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- clock-names: Should contain the following:
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"source" - source clock (required)
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"hclk" - HCLK which used for host (required)
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"source_cg" - independent source clock gate (required for MT2712)
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"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
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- pinctrl-names: should be "default", "state_uhs"
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- pinctrl-0: should contain default/high speed pin ctrl
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- pinctrl-1: should contain uhs mode pin ctrl
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- vmmc-supply: power to the Core
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- vqmmc-supply: power to the IO
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Optional properties:
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- assigned-clocks: PLL of the source clock
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- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
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- hs400-ds-delay: HS400 DS delay setting
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- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
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If present,HS400 command responses are sampled on rising edges.
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If not present,HS400 command responses are sampled on falling edges.
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- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
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error caused by stop clock(fifo full)
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Valid range = [0:0x7]. if not present, default value is 0.
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applied to compatible "mediatek,mt2701-mmc".
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- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
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- reset-names: Should be "hrst".
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Examples:
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
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reg = <0 0x11230000 0 0x108>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clock-names = "source", "hclk";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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hs400-ds-delay = <0x14015>;
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mediatek,hs200-cmd-int-delay = <26>;
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mediatek,hs400-cmd-int-delay = <14>;
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mediatek,hs400-cmd-resp-sel-rising;
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};
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165
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
Normal file
165
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
Normal file
@ -0,0 +1,165 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MTK MSDC Storage Host Controller Binding
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maintainers:
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- Chaotian Jing <chaotian.jing@mediatek.com>
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- Wenbin Mei <wenbin.mei@mediatek.com>
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allOf:
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- $ref: mmc-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-mmc
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- mediatek,mt2712-mmc
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- mediatek,mt6779-mmc
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- mediatek,mt7620-mmc
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- mediatek,mt7622-mmc
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- mediatek,mt8135-mmc
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- mediatek,mt8173-mmc
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- mediatek,mt8183-mmc
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- mediatek,mt8516-mmc
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- items:
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- const: mediatek,mt7623-mmc
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- const: mediatek,mt2701-mmc
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clocks:
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description:
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Should contain phandle for the clock feeding the MMC controller.
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minItems: 2
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maxItems: 4
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items:
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- description: source clock (required).
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- description: HCLK which used for host (required).
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- description: independent source clock gate (required for MT2712).
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- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
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clock-names:
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minItems: 2
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maxItems: 4
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items:
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- const: source
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- const: hclk
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- const: source_cg
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- const: bus_clk
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pinctrl-names:
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items:
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- const: default
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- const: state_uhs
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pinctrl-0:
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description:
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should contain default/high speed pin ctrl.
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maxItems: 1
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pinctrl-1:
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description:
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should contain uhs mode pin ctrl.
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maxItems: 1
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assigned-clocks:
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description:
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PLL of the source clock.
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maxItems: 1
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assigned-clock-parents:
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description:
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parent of source clock, used for HS400 mode to get 400Mhz source clock.
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maxItems: 1
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hs400-ds-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS400 DS delay setting.
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minimum: 0
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maximum: 0xffffffff
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mediatek,hs200-cmd-int-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS200 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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minimum: 0
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maximum: 31
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mediatek,hs400-cmd-int-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS400 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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minimum: 0
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maximum: 31
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mediatek,hs400-cmd-resp-sel-rising:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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HS400 command response sample selection.
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If present, HS400 command responses are sampled on rising edges.
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If not present, HS400 command responses are sampled on falling edges.
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mediatek,latch-ck:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
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data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
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if not present, default value is 0.
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applied to compatible "mediatek,mt2701-mmc".
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minimum: 0
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maximum: 7
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resets:
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maxItems: 1
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reset-names:
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const: hrst
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- pinctrl-names
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- pinctrl-0
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- pinctrl-1
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- vmmc-supply
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- vqmmc-supply
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8173-mmc";
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reg = <0x11230000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clock-names = "source", "hclk";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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hs400-ds-delay = <0x14015>;
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mediatek,hs200-cmd-int-delay = <26>;
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mediatek,hs400-cmd-int-delay = <14>;
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mediatek,hs400-cmd-resp-sel-rising;
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};
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...
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