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drivers/perf: riscv: Align errno for unsupported perf event
RISC-V perf driver does not yet support PERF_TYPE_BREAKPOINT. It would be more appropriate to return -EOPNOTSUPP or -ENOENT for this type in pmu_sbi_event_map. Considering that other implementations return -ENOENT for unsupported perf types, let's synchronize this behavior. Due to this reason, a riscv bpf testcases perf_skip fail. Meanwhile, align that behavior to the rest of proper place. Signed-off-by: Pu Lehui <pulehui@huawei.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Fixes:9b3e150e31
("RISC-V: Add a simple platform driver for RISC-V legacy perf") Fixes:16d3b1af09
("perf: RISC-V: Check standard event availability") Fixes:e999143459
("RISC-V: Add perf platform driver based on SBI PMU extension") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240831071520.1630360-1-pulehui@huaweicloud.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -22,13 +22,13 @@ static int pmu_legacy_ctr_get_idx(struct perf_event *event)
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struct perf_event_attr *attr = &event->attr;
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if (event->attr.type != PERF_TYPE_HARDWARE)
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return -EOPNOTSUPP;
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return -ENOENT;
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if (attr->config == PERF_COUNT_HW_CPU_CYCLES)
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return RISCV_PMU_LEGACY_CYCLE;
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else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)
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return RISCV_PMU_LEGACY_INSTRET;
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else
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return -EOPNOTSUPP;
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return -ENOENT;
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}
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/* For legacy config & counter index are same */
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@ -309,7 +309,7 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata)
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ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
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} else if (ret.error == SBI_ERR_NOT_SUPPORTED) {
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/* This event cannot be monitored by any counter */
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edata->event_idx = -EINVAL;
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edata->event_idx = -ENOENT;
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}
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}
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@ -556,7 +556,7 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
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}
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break;
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default:
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ret = -EINVAL;
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ret = -ENOENT;
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break;
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}
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