From c60f9e29805eb5f27bc7fad088f3becabf388a1c Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Thu, 25 Feb 2016 16:36:34 -0600 Subject: [PATCH] ARM: dts: DRA7: Add TBCLK for PWMSS tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux clock to control ehrpwm tbclk. The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but ehrpwm functional clock derived from the gateable interface and functional clock of PWMSS(l4_root_clk_div). Refer AM57x TRM SPRUHZ6[1], October 2014, Table 29-4 and Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table. [1] www.ti.com/lit/ug/spruhz6/spruhz6.pdf Signed-off-by: Vignesh R Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 357bedeebfac..d0bae06b7eb7 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2146,4 +2146,28 @@ ti,bit-shift = <0>; reg = <0x558>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <20>; + reg = <0x0558>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <21>; + reg = <0x0558>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <22>; + reg = <0x0558>; + }; };