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cciss: switch to pci_irq_alloc_vectors
Simple cleanup to use the new APIs. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Don Brace <don.brace@microsemi.com> Tested-by: Don Brace <don.brace@microsemi.com> Signed-off-by: Jens Axboe <axboe@fb.com>
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@ -4074,41 +4074,27 @@ clean_up:
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static void cciss_interrupt_mode(ctlr_info_t *h)
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{
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#ifdef CONFIG_PCI_MSI
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int err;
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struct msix_entry cciss_msix_entries[4] = { {0, 0}, {0, 1},
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{0, 2}, {0, 3}
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};
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int ret;
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/* Some boards advertise MSI but don't really support it */
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if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
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(h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
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goto default_int_mode;
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if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
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err = pci_enable_msix_exact(h->pdev, cciss_msix_entries, 4);
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if (!err) {
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h->intr[0] = cciss_msix_entries[0].vector;
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h->intr[1] = cciss_msix_entries[1].vector;
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h->intr[2] = cciss_msix_entries[2].vector;
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h->intr[3] = cciss_msix_entries[3].vector;
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h->msix_vector = 1;
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return;
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} else {
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dev_warn(&h->pdev->dev,
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"MSI-X init failed %d\n", err);
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}
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}
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if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
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if (!pci_enable_msi(h->pdev))
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h->msi_vector = 1;
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else
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dev_warn(&h->pdev->dev, "MSI init failed\n");
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ret = pci_alloc_irq_vectors(h->pdev, 4, 4, PCI_IRQ_MSIX);
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if (ret >= 0) {
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h->intr[0] = pci_irq_vector(h->pdev, 0);
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h->intr[1] = pci_irq_vector(h->pdev, 1);
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h->intr[2] = pci_irq_vector(h->pdev, 2);
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h->intr[3] = pci_irq_vector(h->pdev, 3);
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return;
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}
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ret = pci_alloc_irq_vectors(h->pdev, 1, 1, PCI_IRQ_MSI);
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default_int_mode:
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#endif /* CONFIG_PCI_MSI */
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/* if we get here we're going to use the default interrupt mode */
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h->intr[h->intr_mode] = h->pdev->irq;
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h->intr[h->intr_mode] = pci_irq_vector(h->pdev, 0);
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return;
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}
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@ -4888,7 +4874,7 @@ static int cciss_request_irq(ctlr_info_t *h,
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irqreturn_t (*msixhandler)(int, void *),
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irqreturn_t (*intxhandler)(int, void *))
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{
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if (h->msix_vector || h->msi_vector) {
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if (h->pdev->msi_enabled || h->pdev->msix_enabled) {
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if (!request_irq(h->intr[h->intr_mode], msixhandler,
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0, h->devname, h))
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return 0;
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@ -4934,12 +4920,7 @@ static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
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int ctlr = h->ctlr;
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free_irq(h->intr[h->intr_mode], h);
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#ifdef CONFIG_PCI_MSI
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if (h->msix_vector)
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pci_disable_msix(h->pdev);
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else if (h->msi_vector)
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pci_disable_msi(h->pdev);
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#endif /* CONFIG_PCI_MSI */
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pci_free_irq_vectors(h->pdev);
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cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
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cciss_free_scatterlists(h);
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cciss_free_cmd_pool(h);
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@ -5295,12 +5276,7 @@ static void cciss_remove_one(struct pci_dev *pdev)
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cciss_shutdown(pdev);
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#ifdef CONFIG_PCI_MSI
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if (h->msix_vector)
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pci_disable_msix(h->pdev);
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else if (h->msi_vector)
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pci_disable_msi(h->pdev);
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#endif /* CONFIG_PCI_MSI */
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pci_free_irq_vectors(h->pdev);
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iounmap(h->transtable);
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iounmap(h->cfgtable);
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@ -90,8 +90,6 @@ struct ctlr_info
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[4];
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unsigned int msix_vector;
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unsigned int msi_vector;
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int intr_mode;
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int cciss_max_sectors;
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BYTE cciss_read;
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@ -333,7 +331,7 @@ static unsigned long SA5_performant_completed(ctlr_info_t *h)
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*/
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register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
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/* msi auto clears the interrupt pending bit. */
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if (!(h->msi_vector || h->msix_vector)) {
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if (!(h->pdev->msi_enabled || h->pdev->msix_enabled)) {
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writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
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/* Do a read in order to flush the write to the controller
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* (as per spec.)
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@ -393,7 +391,7 @@ static bool SA5_performant_intr_pending(ctlr_info_t *h)
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if (!register_value)
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return false;
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if (h->msi_vector || h->msix_vector)
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if (h->pdev->msi_enabled || h->pdev->msix_enabled)
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return true;
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/* Read outbound doorbell to flush */
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