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EDAC/amd64: Remove early_channel_count()
The early_channel_count() function seems to have been useful in the past for knowing how many EDAC mci structures to populate. However, this is no longer needed as the maximum channel count for a system is used instead. Remove the early_channel_count() helper functions and related code. Use the size of the channel layer when iterating over channel structures. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230127170419.1824692-6-yazen.ghannam@amd.com
This commit is contained in:
Yazen Ghannam
Borislav Petkov (AMD)
parent
cf981562e6
commit
c4605bde33
@ -1703,24 +1703,6 @@ ddr3:
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pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
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}
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/* Get the number of DCT channels the memory controller is using. */
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static int k8_early_channel_count(struct amd64_pvt *pvt)
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{
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int flag;
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if (pvt->ext_model >= K8_REV_F)
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/* RevF (NPT) and later */
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flag = pvt->dclr0 & WIDTH_128;
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else
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/* RevE and earlier */
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flag = pvt->dclr0 & REVE_WIDTH_128;
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/* not used */
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pvt->dclr1 = 0;
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return (flag) ? 2 : 1;
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}
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/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
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static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
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{
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@ -1972,69 +1954,6 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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}
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}
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/*
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* Get the number of DCT channels in use.
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*
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* Return:
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* number of Memory Channels in operation
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* Pass back:
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* contents of the DCL0_LOW register
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*/
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static int f1x_early_channel_count(struct amd64_pvt *pvt)
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{
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int i, j, channels = 0;
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/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
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if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
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return 2;
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/*
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* Need to check if in unganged mode: In such, there are 2 channels,
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* but they are not in 128 bit mode and thus the above 'dclr0' status
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* bit will be OFF.
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*
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* Need to check DCT0[0] and DCT1[0] to see if only one of them has
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* their CSEnable bit on. If so, then SINGLE DIMM case.
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*/
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edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
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/*
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* Check DRAM Bank Address Mapping values for each DIMM to see if there
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* is more than just one DIMM present in unganged mode. Need to check
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* both controllers since DIMMs can be placed in either one.
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*/
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for (i = 0; i < 2; i++) {
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u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
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for (j = 0; j < 4; j++) {
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if (DBAM_DIMM(j, dbam) > 0) {
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channels++;
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break;
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}
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}
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}
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if (channels > 2)
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channels = 2;
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amd64_info("MCT channel count: %d\n", channels);
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return channels;
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}
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static int f17_early_channel_count(struct amd64_pvt *pvt)
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{
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int i, channels = 0;
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/* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */
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for_each_umc(i)
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channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);
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amd64_info("MCT channel count: %d\n", channels);
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return channels;
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}
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static int ddr3_cs_size(unsigned i, bool dct_width)
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{
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unsigned shift = 0;
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@ -2829,7 +2748,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = k8_early_channel_count,
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.map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
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.dbam_to_cs = k8_dbam_to_chip_select,
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}
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@ -2840,7 +2758,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f10_dbam_to_chip_select,
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}
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@ -2851,7 +2768,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f15_dbam_to_chip_select,
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}
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@ -2862,7 +2778,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f16_dbam_to_chip_select,
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}
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@ -2873,7 +2788,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f15_m60h_dbam_to_chip_select,
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}
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@ -2884,7 +2798,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f16_dbam_to_chip_select,
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}
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@ -2895,7 +2808,6 @@ static struct amd64_family_type family_types[] = {
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.f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
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.dbam_to_cs = f16_dbam_to_chip_select,
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}
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@ -2904,7 +2816,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F17h",
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2912,7 +2823,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F17h_M10h",
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2920,7 +2830,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F17h_M30h",
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.max_mcs = 8,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2928,7 +2837,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F17h_M60h",
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2936,7 +2844,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F17h_M70h",
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2944,7 +2851,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F19h",
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.max_mcs = 8,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2953,7 +2859,6 @@ static struct amd64_family_type family_types[] = {
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.max_mcs = 12,
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.flags.zn_regs_v2 = 1,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -2961,7 +2866,6 @@ static struct amd64_family_type family_types[] = {
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.ctl_name = "F19h_M50h",
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.max_mcs = 2,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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@ -3620,7 +3524,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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: EDAC_SECDED;
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}
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for (j = 0; j < pvt->channel_count; j++) {
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for (j = 0; j < fam_type->max_mcs; j++) {
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dimm = csrow->channels[j]->dimm;
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dimm->mtype = pvt->dram_type;
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dimm->edac_mode = edac_mode;
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@ -4057,28 +3961,12 @@ static int init_one_instance(struct amd64_pvt *pvt)
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{
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struct mem_ctl_info *mci = NULL;
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struct edac_mc_layer layers[2];
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int ret = -EINVAL;
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int ret = -ENOMEM;
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/*
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* We need to determine how many memory channels there are. Then use
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* that information for calculating the size of the dynamic instance
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* tables in the 'mci' structure.
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*/
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pvt->channel_count = pvt->ops->early_channel_count(pvt);
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if (pvt->channel_count < 0)
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return ret;
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ret = -ENOMEM;
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = pvt->csels[0].b_cnt;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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/*
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* Always allocate two channels since we can have setups with DIMMs on
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* only one channel. Also, this simplifies handling later for the price
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* of a couple of KBs tops.
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*/
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layers[1].size = fam_type->max_mcs;
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layers[1].is_virt_csrow = false;
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@ -346,7 +346,6 @@ struct amd64_pvt {
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u8 stepping; /* ... stepping */
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int ext_model; /* extended model value of this node */
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int channel_count;
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/* Raw registers */
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u32 dclr0; /* DRAM Configuration Low DCT0 reg */
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@ -466,7 +465,6 @@ struct ecc_settings {
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* functions and per device encoding/decoding logic.
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*/
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struct low_ops {
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int (*early_channel_count) (struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
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struct err_info *);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
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