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dmaengine: dw: rename masters to reflect actual topology
The source and destination masters are reflecting buses or their layers to where the different devices can be connected. The patch changes the master names to reflect which one is related to which independently on the transfer direction. The outcome of the change is that the memory data width is now always limited by a data width of the master which is dedicated to communicate to memory. The patch will not break anything since all current users have the same data width for all masters. Though it would be nice to revisit avr32 platforms to check what is the actual hardware topology in use there. It seems that it has one bus and two masters on it as stated by Table 8-2, that's why everything works independently on the master in use. The purpose of the sequential patch is to fix the driver for configuration of more than one bus. The change is done in the assumption that src_master and dst_master are reflecting a connection to the memory and peripheral correspondently on avr32 and otherwise on the rest. Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -47,8 +47,8 @@ The four cells in order are:
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1. A phandle pointing to the DMA controller
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1. A phandle pointing to the DMA controller
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2. The DMA request line number
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2. The DMA request line number
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3. Source master for transfers on allocated channel
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3. Memory master for transfers on allocated channel
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4. Destination master for transfers on allocated channel
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4. Peripheral master for transfers on allocated channel
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Example:
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Example:
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@ -1365,8 +1365,8 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
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slave->dma_dev = &dw_dmac0_device.dev;
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slave->dma_dev = &dw_dmac0_device.dev;
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slave->src_id = 0;
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slave->src_id = 0;
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slave->dst_id = 1;
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slave->dst_id = 1;
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slave->src_master = 1;
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slave->m_master = 1;
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slave->dst_master = 0;
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slave->p_master = 0;
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data->dma_slave = slave;
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data->dma_slave = slave;
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data->dma_filter = at32_mci_dma_filter;
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data->dma_filter = at32_mci_dma_filter;
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@ -2061,16 +2061,16 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
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if (flags & AC97C_CAPTURE) {
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if (flags & AC97C_CAPTURE) {
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rx_dws->dma_dev = &dw_dmac0_device.dev;
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rx_dws->dma_dev = &dw_dmac0_device.dev;
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rx_dws->src_id = 3;
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rx_dws->src_id = 3;
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rx_dws->src_master = 0;
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rx_dws->m_master = 0;
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rx_dws->dst_master = 1;
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rx_dws->p_master = 1;
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}
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}
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/* Check if DMA slave interface for playback should be configured. */
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/* Check if DMA slave interface for playback should be configured. */
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if (flags & AC97C_PLAYBACK) {
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if (flags & AC97C_PLAYBACK) {
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tx_dws->dma_dev = &dw_dmac0_device.dev;
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tx_dws->dma_dev = &dw_dmac0_device.dev;
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tx_dws->dst_id = 4;
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tx_dws->dst_id = 4;
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tx_dws->src_master = 0;
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tx_dws->m_master = 0;
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tx_dws->dst_master = 1;
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tx_dws->p_master = 1;
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}
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}
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if (platform_device_add_data(pdev, data,
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if (platform_device_add_data(pdev, data,
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@ -2141,8 +2141,8 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
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dws->dma_dev = &dw_dmac0_device.dev;
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dws->dma_dev = &dw_dmac0_device.dev;
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dws->dst_id = 2;
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dws->dst_id = 2;
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dws->src_master = 0;
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dws->m_master = 0;
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dws->dst_master = 1;
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dws->p_master = 1;
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if (platform_device_add_data(pdev, data,
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if (platform_device_add_data(pdev, data,
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sizeof(struct atmel_abdac_pdata)))
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sizeof(struct atmel_abdac_pdata)))
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@ -201,8 +201,8 @@ static struct sata_dwc_host_priv host_pvt;
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static struct dw_dma_slave sata_dwc_dma_dws = {
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static struct dw_dma_slave sata_dwc_dma_dws = {
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.src_id = 0,
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.src_id = 0,
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.dst_id = 0,
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.dst_id = 0,
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.src_master = 0,
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.m_master = 1,
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.dst_master = 1,
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.p_master = 0,
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};
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};
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/*
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/*
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@ -50,8 +50,8 @@
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| DWC_CTLL_SRC_MSIZE(_smsize) \
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| DWC_CTLL_SRC_MSIZE(_smsize) \
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| DWC_CTLL_LLP_D_EN \
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| DWC_CTLL_LLP_D_EN \
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| DWC_CTLL_LLP_S_EN \
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| DWC_CTLL_LLP_S_EN \
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| DWC_CTLL_DMS(_dwc->dst_master) \
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| DWC_CTLL_DMS(_dwc->p_master) \
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| DWC_CTLL_SMS(_dwc->src_master)); \
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| DWC_CTLL_SMS(_dwc->m_master)); \
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})
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})
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/*
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/*
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@ -709,8 +709,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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dwc->direction = DMA_MEM_TO_MEM;
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dwc->direction = DMA_MEM_TO_MEM;
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data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
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data_width = dw->data_width[dwc->m_master];
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dw->data_width[dwc->dst_master]);
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src_width = dst_width = min_t(unsigned int, data_width,
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src_width = dst_width = min_t(unsigned int, data_width,
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dwc_fast_ffs(src | dest | len));
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dwc_fast_ffs(src | dest | len));
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@ -802,7 +801,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
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DWC_CTLL_FC(DW_DMA_FC_D_M2P);
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DWC_CTLL_FC(DW_DMA_FC_D_M2P);
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data_width = dw->data_width[dwc->src_master];
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data_width = dw->data_width[dwc->m_master];
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for_each_sg(sgl, sg, sg_len, i) {
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for_each_sg(sgl, sg, sg_len, i) {
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struct dw_desc *desc;
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struct dw_desc *desc;
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@ -859,7 +858,7 @@ slave_sg_todev_fill_desc:
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
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DWC_CTLL_FC(DW_DMA_FC_D_P2M);
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DWC_CTLL_FC(DW_DMA_FC_D_P2M);
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data_width = dw->data_width[dwc->dst_master];
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data_width = dw->data_width[dwc->m_master];
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for_each_sg(sgl, sg, sg_len, i) {
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for_each_sg(sgl, sg, sg_len, i) {
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struct dw_desc *desc;
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struct dw_desc *desc;
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@ -937,8 +936,8 @@ bool dw_dma_filter(struct dma_chan *chan, void *param)
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dwc->src_id = dws->src_id;
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dwc->src_id = dws->src_id;
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dwc->dst_id = dws->dst_id;
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dwc->dst_id = dws->dst_id;
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dwc->src_master = dws->src_master;
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dwc->m_master = dws->m_master;
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dwc->dst_master = dws->dst_master;
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dwc->p_master = dws->p_master;
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return true;
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return true;
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}
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}
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@ -1227,8 +1226,8 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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dwc->src_id = 0;
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dwc->src_id = 0;
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dwc->dst_id = 0;
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dwc->dst_id = 0;
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dwc->src_master = 0;
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dwc->m_master = 0;
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dwc->dst_master = 0;
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dwc->p_master = 0;
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dwc->initialized = false;
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dwc->initialized = false;
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@ -42,13 +42,13 @@ static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
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slave.src_id = dma_spec->args[0];
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slave.src_id = dma_spec->args[0];
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slave.dst_id = dma_spec->args[0];
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slave.dst_id = dma_spec->args[0];
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slave.src_master = dma_spec->args[1];
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slave.m_master = dma_spec->args[1];
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slave.dst_master = dma_spec->args[2];
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slave.p_master = dma_spec->args[2];
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if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
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if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
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slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
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slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
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slave.src_master >= dw->nr_masters ||
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slave.m_master >= dw->nr_masters ||
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slave.dst_master >= dw->nr_masters))
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slave.p_master >= dw->nr_masters))
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return NULL;
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return NULL;
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dma_cap_zero(cap);
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dma_cap_zero(cap);
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@ -66,8 +66,8 @@ static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
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.dma_dev = dma_spec->dev,
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.dma_dev = dma_spec->dev,
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.src_id = dma_spec->slave_id,
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.src_id = dma_spec->slave_id,
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.dst_id = dma_spec->slave_id,
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.dst_id = dma_spec->slave_id,
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.src_master = 1,
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.m_master = 0,
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.dst_master = 0,
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.p_master = 1,
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};
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};
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return dw_dma_filter(chan, &slave);
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return dw_dma_filter(chan, &slave);
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@ -249,8 +249,8 @@ struct dw_dma_chan {
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/* custom slave configuration */
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/* custom slave configuration */
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u8 src_id;
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u8 src_id;
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u8 dst_id;
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u8 dst_id;
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u8 src_master;
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u8 m_master;
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u8 dst_master;
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u8 p_master;
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/* configuration passed via .device_config */
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/* configuration passed via .device_config */
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struct dma_slave_config dma_sconfig;
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struct dma_slave_config dma_sconfig;
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@ -144,16 +144,16 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
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struct dw_dma_slave *slave = c->tx_param;
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struct dw_dma_slave *slave = c->tx_param;
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slave->dma_dev = &dma_dev->dev;
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slave->dma_dev = &dma_dev->dev;
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slave->src_master = 1;
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slave->m_master = 0;
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slave->dst_master = 0;
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slave->p_master = 1;
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}
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}
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if (c->rx_param) {
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if (c->rx_param) {
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struct dw_dma_slave *slave = c->rx_param;
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struct dw_dma_slave *slave = c->rx_param;
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slave->dma_dev = &dma_dev->dev;
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slave->dma_dev = &dma_dev->dev;
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slave->src_master = 1;
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slave->m_master = 0;
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slave->dst_master = 0;
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slave->p_master = 1;
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}
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}
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spi_pdata.dma_filter = lpss_dma_filter;
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spi_pdata.dma_filter = lpss_dma_filter;
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@ -1454,13 +1454,13 @@ byt_serial_setup(struct serial_private *priv,
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return -EINVAL;
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return -EINVAL;
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}
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}
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rx_param->src_master = 1;
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rx_param->m_master = 0;
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rx_param->dst_master = 0;
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rx_param->p_master = 1;
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dma->rxconf.src_maxburst = 16;
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dma->rxconf.src_maxburst = 16;
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tx_param->src_master = 1;
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tx_param->m_master = 0;
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tx_param->dst_master = 0;
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tx_param->p_master = 1;
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dma->txconf.dst_maxburst = 16;
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dma->txconf.dst_maxburst = 16;
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@ -21,15 +21,15 @@
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* @dma_dev: required DMA master device
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* @dma_dev: required DMA master device
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* @src_id: src request line
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* @src_id: src request line
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* @dst_id: dst request line
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* @dst_id: dst request line
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* @src_master: src master for transfers on allocated channel.
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* @m_master: memory master for transfers on allocated channel
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* @dst_master: dest master for transfers on allocated channel.
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* @p_master: peripheral master for transfers on allocated channel
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*/
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*/
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struct dw_dma_slave {
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struct dw_dma_slave {
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struct device *dma_dev;
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struct device *dma_dev;
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u8 src_id;
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u8 src_id;
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u8 dst_id;
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u8 dst_id;
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u8 src_master;
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u8 m_master;
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u8 dst_master;
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u8 p_master;
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};
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};
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/**
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/**
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