mirror of
https://github.com/torvalds/linux.git
synced 2024-11-21 19:41:42 +00:00
SoC: DT changes for 6.8
There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
already supported chips.
The other six new SoCs are all part of existing arm64 families, but
are somewhat more interesting:
- Samsung ExynosAutov920 is an automotive chip, and the first one
we support based on the Cortex-A78AE core with lockstep mode.
- Google gs101 (Tensor G1) is the chip used in a number of Pixel phones,
and is grouped with Samsung Exynos here since it is based on the same
SoC design, sharing most of its IP blocks with that series.
- MediaTek MT8188 is a new chip used for mid-range tablets and Chromebooks,
using two Cortex-A78 cores where the older MT8195 had four of them.
- Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
phone SoC and the first supported chip based on Cortex-X4, Cortex-A720
and Cortex-A520.
- Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest
Laptop chip using the custom Oryon cores.
- Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
Cortex-A76 and Cortex-A55
In terms of boards, we have
- Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.
- Multiple Rockchips mobile gaming systems (Anbernic RG351V,
Powkiddy RK2023, Powkiddy X55) along with the Sonoff iHost Smart
Home Hub and a few Rockchips SBCs
- Some ComXpress boards based on Marvell CN913x, which is the
follow-up to Armada 7xxx/8xxx.
- Six new industrial/embedded boards based on NXP i.MX8 and i.MX9
- Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.
- Toradex Verdin AM62 Mallow carrier for TI AM62
- Huashan Pi board based on the SophGo CV1812H RISC-V chip
- Two boards based on Allwinner H616/H618
- A number of reference boards for various added SoCs from Qualcomm,
Mediatek, Google, Samsung, NXP and Spreadtrum
As usual, there are cleanups and warning fixes across all platforms as
well as added features for several of them.
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Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
already supported chips.
The other six new SoCs are all part of existing arm64 families, but
are somewhat more interesting:
- Samsung ExynosAutov920 is an automotive chip, and the first one we
support based on the Cortex-A78AE core with lockstep mode.
- Google gs101 (Tensor G1) is the chip used in a number of Pixel
phones, and is grouped with Samsung Exynos here since it is based
on the same SoC design, sharing most of its IP blocks with that
series.
- MediaTek MT8188 is a new chip used for mid-range tablets and
Chromebooks, using two Cortex-A78 cores where the older MT8195 had
four of them.
- Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
phone SoC and the first supported chip based on Cortex-X4,
Cortex-A720 and Cortex-A520.
- Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop
chip using the custom Oryon cores.
- Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
Cortex-A76 and Cortex-A55
In terms of boards, we have
- Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.
- Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy
RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub
and a few Rockchips SBCs
- Some ComXpress boards based on Marvell CN913x, which is the
follow-up to Armada 7xxx/8xxx.
- Six new industrial/embedded boards based on NXP i.MX8 and i.MX9
- Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.
- Toradex Verdin AM62 Mallow carrier for TI AM62
- Huashan Pi board based on the SophGo CV1812H RISC-V chip
- Two boards based on Allwinner H616/H618
- A number of reference boards for various added SoCs from Qualcomm,
Mediatek, Google, Samsung, NXP and Spreadtrum
As usual, there are cleanups and warning fixes across all platforms as
well as added features for several of them"
* tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits)
ARM: dts: usr8200: Fix phy registers
arm64: dts: intel: minor whitespace cleanup around '='
arm64: dts: socfpga: agilex: drop redundant status
arm64: dts: socfpga: agilex: add unit address to soc node
arm64: dts: socfpga: agilex: move firmware out of soc node
arm64: dts: socfpga: agilex: move FPGA region out of soc node
arm64: dts: socfpga: agilex: align pin-controller name with bindings
arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
arm64: dts: socfpga: stratix10: add unit address to soc node
arm64: dts: socfpga: stratix10: move firmware out of soc node
arm64: dts: socfpga: stratix10: move FPGA region out of soc node
arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
ARM: dts: socfpga: align NAND controller name with bindings
ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
arm64: dts: rockchip: Fix led pinctrl of lubancat 1
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
...
This commit is contained in:
Linus Torvalds
commit
c4101e5597
@ -198,6 +198,7 @@ properties:
|
||||
- qcom,kryo660
|
||||
- qcom,kryo685
|
||||
- qcom,kryo780
|
||||
- qcom,oryon
|
||||
- qcom,scorpion
|
||||
|
||||
enable-method:
|
||||
|
||||
@ -967,6 +967,7 @@ properties:
|
||||
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
|
||||
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
|
||||
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
|
||||
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
|
||||
@ -977,6 +978,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
|
||||
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
|
||||
@ -1022,7 +1024,10 @@ properties:
|
||||
|
||||
- description: Variscite VAR-SOM-MX8MN based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx8mn-symphony
|
||||
- enum:
|
||||
- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
|
||||
- rve,rve-gateway # i.MX8MN RVE Gateway Board
|
||||
- variscite,var-som-mx8mn-symphony
|
||||
- const: variscite,var-som-mx8mn
|
||||
- const: fsl,imx8mn
|
||||
|
||||
@ -1048,6 +1053,9 @@ properties:
|
||||
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
|
||||
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
|
||||
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
|
||||
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
|
||||
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
|
||||
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
|
||||
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
|
||||
@ -1100,6 +1108,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
|
||||
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
|
||||
- toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
|
||||
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
|
||||
@ -1110,6 +1119,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
|
||||
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
|
||||
@ -1476,6 +1486,16 @@ properties:
|
||||
- const: solidrun,lx2162a-som
|
||||
- const: fsl,lx2160a
|
||||
|
||||
- description:
|
||||
TQ-Systems TQMLX2160A is a series of socketable SOM featuring
|
||||
LX2160A system-on-chip variants. MBLX2160A mainboard can be used a
|
||||
starterkit.
|
||||
items:
|
||||
- enum:
|
||||
- tq,lx2160a-tqmlx2160a-mblx2160a
|
||||
- const: tq,lx2160a-tqmlx2160a
|
||||
- const: fsl,lx2160a
|
||||
|
||||
- description: S32G2 based Boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
53
Documentation/devicetree/bindings/arm/google.yaml
Normal file
53
Documentation/devicetree/bindings/arm/google.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/google.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Google Tensor platforms
|
||||
|
||||
maintainers:
|
||||
- Peter Griffin <peter.griffin@linaro.org>
|
||||
|
||||
description: |
|
||||
ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
|
||||
devices.
|
||||
|
||||
Currently upstream this is devices using "gs101" SoC which is found in Pixel
|
||||
6, Pixel 6 Pro and Pixel 6a.
|
||||
|
||||
Google have a few different names for the SoC:
|
||||
- Marketing name ("Tensor")
|
||||
- Codename ("Whitechapel")
|
||||
- SoC ID ("gs101")
|
||||
- Die ID ("S5P9845")
|
||||
|
||||
Likewise there are a couple of names for the actual device
|
||||
- Marketing name ("Pixel 6")
|
||||
- Codename ("Oriole")
|
||||
|
||||
Devicetrees should use the lowercased SoC ID and lowercased board codename,
|
||||
e.g. gs101 and gs101-oriole.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Google Pixel 6 / Oriole
|
||||
items:
|
||||
- enum:
|
||||
- google,gs101-oriole
|
||||
- const: google,gs101
|
||||
|
||||
# Bootloader requires empty ect node to be present
|
||||
ect:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- ect
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -82,6 +82,23 @@ properties:
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
'^clock@':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- hisilicon,hi3620-clock
|
||||
- hisilicon,hi3620-mmc-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -60,4 +60,26 @@ properties:
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description:
|
||||
Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
|
||||
Armada CN9130 COM Express CPU module
|
||||
items:
|
||||
- const: marvell,cn9130-ac5x-carrier
|
||||
- const: marvell,rd-ac5x-carrier
|
||||
- const: marvell,cn9130-cpu-module
|
||||
- const: marvell,cn9130
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description:
|
||||
Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
|
||||
Armada CN9131 COM Express CPU module
|
||||
items:
|
||||
- const: marvell,cn9131-ac5x-carrier
|
||||
- const: marvell,rd-ac5x-carrier
|
||||
- const: marvell,cn9131-cpu-module
|
||||
- const: marvell,cn9131
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -174,6 +174,10 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8186-evb
|
||||
- const: mediatek,mt8186
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-evb
|
||||
- const: mediatek,mt8188
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8192-evb
|
||||
@ -235,6 +239,13 @@ properties:
|
||||
items:
|
||||
- const: google,kappa
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Katsu (ASUS Chromebook Detachable CZ1)
|
||||
items:
|
||||
- enum:
|
||||
- google,katsu-sku32
|
||||
- google,katsu-sku38
|
||||
- const: google,katsu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
|
||||
items:
|
||||
- enum:
|
||||
@ -244,6 +255,20 @@ properties:
|
||||
- google,kodama-sku32
|
||||
- const: google,kodama
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
|
||||
items:
|
||||
- enum:
|
||||
- google,makomo-sku0
|
||||
- google,makomo-sku1
|
||||
- const: google,makomo
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Pico (Acer Chromebook Spin 311)
|
||||
items:
|
||||
- enum:
|
||||
- google,pico-sku1
|
||||
- google,pico-sku2
|
||||
- const: google,pico
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Willow (Acer Chromebook 311 C722/C722T)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
MediaTek AUDSYS controller
|
||||
============================
|
||||
|
||||
The MediaTek AUDSYS controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt6765-audsys", "syscon"
|
||||
- "mediatek,mt6779-audio", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt8167-audiosys", "syscon"
|
||||
- "mediatek,mt8183-audiosys", "syscon"
|
||||
- "mediatek,mt8192-audsys", "syscon"
|
||||
- "mediatek,mt8516-audsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The AUDSYS controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Required sub-nodes:
|
||||
-------
|
||||
For common binding part and usage, refer to
|
||||
../sonud/mt2701-afe-pcm.txt.
|
||||
|
||||
Example:
|
||||
|
||||
audsys: clock-controller@11220000 {
|
||||
compatible = "mediatek,mt7622-audsys", "syscon";
|
||||
reg = <0 0x11220000 0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
afe: audio-controller {
|
||||
...
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,153 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek AUDSYS controller
|
||||
|
||||
maintainers:
|
||||
- Eugen Hristev <eugen.hristev@collabora.com>
|
||||
|
||||
description:
|
||||
The MediaTek AUDSYS controller provides various clocks to the system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-audsys
|
||||
- mediatek,mt6765-audsys
|
||||
- mediatek,mt6779-audsys
|
||||
- mediatek,mt7622-audsys
|
||||
- mediatek,mt8167-audsys
|
||||
- mediatek,mt8173-audsys
|
||||
- mediatek,mt8183-audsys
|
||||
- mediatek,mt8186-audsys
|
||||
- mediatek,mt8192-audsys
|
||||
- mediatek,mt8516-audsys
|
||||
- const: syscon
|
||||
- items:
|
||||
# Special case for mt7623 for backward compatibility
|
||||
- const: mediatek,mt7623-audsys
|
||||
- const: mediatek,mt2701-audsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
audio-controller:
|
||||
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/mt2701-power.h>
|
||||
#include <dt-bindings/clock/mt2701-clk.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
audsys: clock-controller@11220000 {
|
||||
compatible = "mediatek,mt7622-audsys", "syscon";
|
||||
reg = <0 0x11220000 0 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
afe: audio-controller {
|
||||
compatible = "mediatek,mt2701-audio";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "afe", "asys";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
||||
|
||||
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
||||
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_48K_TIMING>,
|
||||
<&topckgen CLK_TOP_AUD_44K_TIMING>,
|
||||
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
|
||||
<&audsys CLK_AUD_I2SO1>,
|
||||
<&audsys CLK_AUD_I2SO2>,
|
||||
<&audsys CLK_AUD_I2SO3>,
|
||||
<&audsys CLK_AUD_I2SO4>,
|
||||
<&audsys CLK_AUD_I2SIN1>,
|
||||
<&audsys CLK_AUD_I2SIN2>,
|
||||
<&audsys CLK_AUD_I2SIN3>,
|
||||
<&audsys CLK_AUD_I2SIN4>,
|
||||
<&audsys CLK_AUD_ASRCO1>,
|
||||
<&audsys CLK_AUD_ASRCO2>,
|
||||
<&audsys CLK_AUD_ASRCO3>,
|
||||
<&audsys CLK_AUD_ASRCO4>,
|
||||
<&audsys CLK_AUD_AFE>,
|
||||
<&audsys CLK_AUD_AFE_CONN>,
|
||||
<&audsys CLK_AUD_A1SYS>,
|
||||
<&audsys CLK_AUD_A2SYS>,
|
||||
<&audsys CLK_AUD_AFE_MRGIF>;
|
||||
|
||||
clock-names = "infra_sys_audio_clk",
|
||||
"top_audio_mux1_sel",
|
||||
"top_audio_mux2_sel",
|
||||
"top_audio_a1sys_hp",
|
||||
"top_audio_a2sys_hp",
|
||||
"i2s0_src_sel",
|
||||
"i2s1_src_sel",
|
||||
"i2s2_src_sel",
|
||||
"i2s3_src_sel",
|
||||
"i2s0_src_div",
|
||||
"i2s1_src_div",
|
||||
"i2s2_src_div",
|
||||
"i2s3_src_div",
|
||||
"i2s0_mclk_en",
|
||||
"i2s1_mclk_en",
|
||||
"i2s2_mclk_en",
|
||||
"i2s3_mclk_en",
|
||||
"i2so0_hop_ck",
|
||||
"i2so1_hop_ck",
|
||||
"i2so2_hop_ck",
|
||||
"i2so3_hop_ck",
|
||||
"i2si0_hop_ck",
|
||||
"i2si1_hop_ck",
|
||||
"i2si2_hop_ck",
|
||||
"i2si3_hop_ck",
|
||||
"asrc0_out_ck",
|
||||
"asrc1_out_ck",
|
||||
"asrc2_out_ck",
|
||||
"asrc3_out_ck",
|
||||
"audio_afe_pd",
|
||||
"audio_afe_conn_pd",
|
||||
"audio_a1sys_pd",
|
||||
"audio_a2sys_pd",
|
||||
"audio_mrgif_pd";
|
||||
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
|
||||
<&topckgen CLK_TOP_AUD2PLL_90M>;
|
||||
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -32,6 +32,9 @@ properties:
|
||||
- mediatek,mt8183-mmsys
|
||||
- mediatek,mt8186-mmsys
|
||||
- mediatek,mt8188-vdosys0
|
||||
- mediatek,mt8188-vdosys1
|
||||
- mediatek,mt8188-vppsys0
|
||||
- mediatek,mt8188-vppsys1
|
||||
- mediatek,mt8192-mmsys
|
||||
- mediatek,mt8195-vdosys1
|
||||
- mediatek,mt8195-vppsys0
|
||||
|
||||
@ -28,6 +28,7 @@ properties:
|
||||
- mediatek,mt8173-pericfg
|
||||
- mediatek,mt8183-pericfg
|
||||
- mediatek,mt8186-pericfg
|
||||
- mediatek,mt8188-pericfg
|
||||
- mediatek,mt8195-pericfg
|
||||
- mediatek,mt8516-pericfg
|
||||
- const: syscon
|
||||
|
||||
@ -23,7 +23,7 @@ description: |
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -31,17 +31,17 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
# Preferred naming style for compatibles of SoC components:
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
|
||||
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
|
||||
|
||||
# Legacy namings - variations of existing patterns/compatibles are OK,
|
||||
# but do not add completely new entries to these:
|
||||
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
|
||||
- enum:
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
- qcom,gpucc-sdm630
|
||||
|
||||
@ -87,29 +87,18 @@ description: |
|
||||
sm8350
|
||||
sm8450
|
||||
sm8550
|
||||
sm8650
|
||||
x1e80100
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
adp
|
||||
ap-al02-c2
|
||||
ap-al02-c6
|
||||
ap-al02-c7
|
||||
ap-al02-c8
|
||||
ap-al02-c9
|
||||
ap-mi01.2
|
||||
ap-mi01.3
|
||||
ap-mi01.6
|
||||
ap-mi01.9
|
||||
cdp
|
||||
cp01-c1
|
||||
dragonboard
|
||||
hk01
|
||||
hk10-c1
|
||||
hk10-c2
|
||||
idp
|
||||
liquid
|
||||
rdp432-c2
|
||||
mtp
|
||||
qcp
|
||||
qrd
|
||||
rb2
|
||||
ride
|
||||
@ -138,7 +127,7 @@ description: |
|
||||
There are many devices in the list below that run the standard ChromeOS
|
||||
bootloader setup and use the open source depthcharge bootloader to boot the
|
||||
OS. These devices do not use the scheme described above. For details, see:
|
||||
https://docs.kernel.org/arm/google/chromebook-boot-flow.html
|
||||
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
@ -186,11 +175,24 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- microsoft,dempsey
|
||||
- microsoft,makepeace
|
||||
- microsoft,moneypenny
|
||||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- htc,memul
|
||||
- microsoft,superman-lte
|
||||
- microsoft,tesla
|
||||
- motorola,peregrine
|
||||
- const: qcom,msm8926
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- huawei,kiwi
|
||||
- longcheer,l9100
|
||||
- samsung,a7
|
||||
- sony,kanuti-tulip
|
||||
@ -397,6 +399,8 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp5
|
||||
- qcom,qcm6490-idp
|
||||
- qcom,qcs6490-rb3gen2
|
||||
- const: qcom,qcm6490
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
|
||||
@ -1009,6 +1013,7 @@ properties:
|
||||
- sony,pdx203-generic
|
||||
- sony,pdx206-generic
|
||||
- xiaomi,elish
|
||||
- xiaomi,pipa
|
||||
- const: qcom,sm8250
|
||||
|
||||
- items:
|
||||
@ -1034,6 +1039,18 @@ properties:
|
||||
- qcom,sm8550-qrd
|
||||
- const: qcom,sm8550
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8650-mtp
|
||||
- qcom,sm8650-qrd
|
||||
- const: qcom,sm8650
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,x1e80100-crd
|
||||
- qcom,x1e80100-qcp
|
||||
- const: qcom,x1e80100
|
||||
|
||||
# Board compatibles go above
|
||||
|
||||
qcom,msm-id:
|
||||
|
||||
@ -30,9 +30,11 @@ properties:
|
||||
- const: amarula,vyasa-rk3288
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Anbernic RG351M
|
||||
- description: Anbernic RK3326 Handheld Gaming Console
|
||||
items:
|
||||
- const: anbernic,rg351m
|
||||
- enum:
|
||||
- anbernic,rg351m
|
||||
- anbernic,rg351v
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Anbernic RG353P
|
||||
@ -95,22 +97,30 @@ properties:
|
||||
- const: chipspark,rayeager-px2
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Cool Pi Compute Module 5(CM5) EVB
|
||||
items:
|
||||
- enum:
|
||||
- coolpi,pi-cm5-evb
|
||||
- const: coolpi,pi-cm5
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Cool Pi 4 Model B
|
||||
items:
|
||||
- const: coolpi,pi-4b
|
||||
- const: rockchip,rk3588s
|
||||
|
||||
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
|
||||
items:
|
||||
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
|
||||
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
|
||||
- const: rockchip,rv1126
|
||||
|
||||
- description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
|
||||
- description: Edgeble Neural Compute Module 6(Neu6) SoM based boards
|
||||
items:
|
||||
- const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
|
||||
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
|
||||
items:
|
||||
- const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board
|
||||
- const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
|
||||
- const: edgeble,neural-compute-module-6a-io # Edgeble NCM6A-IO Board
|
||||
- enum:
|
||||
- edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
|
||||
- edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Elgin RV1108 R1
|
||||
@ -237,6 +247,11 @@ properties:
|
||||
- const: geekbuying,geekbox
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Geniatech XPI-3128
|
||||
items:
|
||||
- const: geniatech,xpi-3128
|
||||
- const: rockchip,rk3128
|
||||
|
||||
- description: Google Bob (Asus Chromebook Flip C101PA)
|
||||
items:
|
||||
- const: google,bob-rev13
|
||||
@ -674,9 +689,12 @@ properties:
|
||||
- const: pine64,soquartz
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Powkiddy RGB30
|
||||
- description: Powkiddy RK3566 Handheld Gaming Console
|
||||
items:
|
||||
- const: powkiddy,rgb30
|
||||
- enum:
|
||||
- powkiddy,rgb30
|
||||
- powkiddy,rk2023
|
||||
- powkiddy,x55
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Radxa Compute Module 3(CM3)
|
||||
@ -875,6 +893,11 @@ properties:
|
||||
- const: tsd,rk3399-puma-haikou
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Theobroma Systems RK3588-SBC Jaguar
|
||||
items:
|
||||
- const: tsd,rk3588-jaguar
|
||||
- const: rockchip,rk3588
|
||||
|
||||
- description: Tronsmart Orion R68 Meta
|
||||
items:
|
||||
- const: tronsmart,orion-r68-meta
|
||||
@ -922,6 +945,13 @@ properties:
|
||||
- const: rockchip,rk3568-bpi-r2pro
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Sonoff iHost Smart Home Hub
|
||||
items:
|
||||
- const: itead,sonoff-ihost
|
||||
- enum:
|
||||
- rockchip,rv1126
|
||||
- rockchip,rv1109
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -230,6 +230,12 @@ properties:
|
||||
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
|
||||
- const: samsung,exynosautov9
|
||||
|
||||
- description: Exynos Auto v920 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK
|
||||
- const: samsung,exynosautov920
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
||||
@ -35,6 +35,11 @@ properties:
|
||||
- sprd,ums512-1h10
|
||||
- const: sprd,ums512
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,ums9620-2h10
|
||||
- const: sprd,ums9620
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -82,29 +82,19 @@ properties:
|
||||
- shiratech,stm32mp157a-iot-box # IoT Box
|
||||
- shiratech,stm32mp157a-stinger96 # Stinger96
|
||||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157c-ed1-scmi
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157a-dk1-scmi
|
||||
- st,stm32mp157c-dk2
|
||||
- st,stm32mp157c-dk2-scmi
|
||||
- const: st,stm32mp157
|
||||
|
||||
- items:
|
||||
- const: st,stm32mp157a-dk1-scmi
|
||||
- const: st,stm32mp157a-dk1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-dk2-scmi
|
||||
- const: st,stm32mp157c-dk2
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ed1-scmi
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1-scmi
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
|
||||
|
||||
@ -868,6 +868,11 @@ properties:
|
||||
- const: topwise,a721
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: Transpeed 8K618-T
|
||||
items:
|
||||
- const: transpeed,8k618-t
|
||||
- const: allwinner,sun50i-h618
|
||||
|
||||
- description: Utoo P66
|
||||
items:
|
||||
- const: utoo,p66
|
||||
@ -1013,6 +1018,11 @@ properties:
|
||||
- const: xunlong,orangepi-zero2
|
||||
- const: allwinner,sun50i-h616
|
||||
|
||||
- description: Xunlong OrangePi Zero 2W
|
||||
items:
|
||||
- const: xunlong,orangepi-zero2w
|
||||
- const: allwinner,sun50i-h618
|
||||
|
||||
- description: Xunlong OrangePi Zero 3
|
||||
items:
|
||||
- const: xunlong,orangepi-zero3
|
||||
|
||||
@ -50,6 +50,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
|
||||
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
|
||||
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
|
||||
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
|
||||
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-am62 # Verdin AM62 Module
|
||||
@ -60,6 +61,7 @@ properties:
|
||||
- enum:
|
||||
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
|
||||
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
|
||||
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
|
||||
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
|
||||
- const: toradex,verdin-am62 # Verdin AM62 Module
|
||||
|
||||
@ -134,6 +134,8 @@ properties:
|
||||
- amazon,omap4-kc1 # Amazon Kindle Fire (first generation)
|
||||
- motorola,droid4 # Motorola Droid 4 XT894
|
||||
- motorola,droid-bionic # Motorola Droid Bionic XT875
|
||||
- motorola,xyboard-mz609
|
||||
- motorola,xyboard-mz617
|
||||
- ti,omap4-panda
|
||||
- ti,omap4-sdp
|
||||
- const: ti,omap4430
|
||||
|
||||
106
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
Normal file
106
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
Normal file
@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Google GS101 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Peter Griffin <peter.griffin@linaro.org>
|
||||
|
||||
description: |
|
||||
Google GS101 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that clock tree
|
||||
is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
|
||||
clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'dt-bindings/clock/gs101.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- google,gs101-cmu-top
|
||||
- google,gs101-cmu-apm
|
||||
- google,gs101-cmu-misc
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-cmu-top
|
||||
- google,gs101-cmu-apm
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24.576 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: google,gs101-cmu-misc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Misc bus clock (from CMU_TOP)
|
||||
- description: Misc sss clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: dout_cmu_misc_bus
|
||||
- const: dout_cmu_misc_sss
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_TOP
|
||||
- |
|
||||
#include <dt-bindings/clock/google,gs101.h>
|
||||
|
||||
cmu_top: clock-controller@1e080000 {
|
||||
compatible = "google,gs101-cmu-top";
|
||||
reg = <0x1e080000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ext_24_5m>;
|
||||
clock-names = "oscclk";
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,20 +0,0 @@
|
||||
* Hisilicon Hi3620 Clock Controller
|
||||
|
||||
The Hi3620 clock controller generates and supplies clock to various
|
||||
controllers within the Hi3620 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
|
||||
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.
|
||||
@ -43,8 +43,6 @@ properties:
|
||||
- mediatek,mt8188-vdecsys
|
||||
- mediatek,mt8188-vdecsys-soc
|
||||
- mediatek,mt8188-vencsys
|
||||
- mediatek,mt8188-vppsys0
|
||||
- mediatek,mt8188-vppsys1
|
||||
- mediatek,mt8188-wpesys
|
||||
- mediatek,mt8188-wpesys-vpp0
|
||||
|
||||
|
||||
@ -15,6 +15,9 @@ description: |
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-camcc
|
||||
@ -33,15 +36,6 @@ properties:
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: MMCX power domain
|
||||
@ -56,14 +50,10 @@ properties:
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -27,11 +27,15 @@ properties:
|
||||
items:
|
||||
- description: board XO clock
|
||||
- description: sleep clock
|
||||
- description: Gen3 QMP PCIe PHY PIPE clock
|
||||
- description: Gen2 QMP PCIe PHY PIPE clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: pcie0_pipe
|
||||
- const: pcie1_pipe
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -35,6 +35,8 @@ properties:
|
||||
- qcom,sm8350-rpmh-clk
|
||||
- qcom,sm8450-rpmh-clk
|
||||
- qcom,sm8550-rpmh-clk
|
||||
- qcom,sm8650-rpmh-clk
|
||||
- qcom,x1e80100-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
@ -15,6 +15,9 @@ description: |
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-camcc
|
||||
@ -31,28 +34,15 @@ properties:
|
||||
- const: iface
|
||||
- const: xo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -15,6 +15,9 @@ description: |
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7280-camcc
|
||||
@ -31,28 +34,15 @@ properties:
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -15,6 +15,9 @@ description: |
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-camcc
|
||||
@ -27,28 +30,15 @@ properties:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -16,10 +16,15 @@ description: |
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-camcc.h
|
||||
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-camcc
|
||||
- qcom,sm8450-camcc
|
||||
- qcom,sm8550-camcc
|
||||
|
||||
@ -40,29 +45,16 @@ properties:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- power-domains
|
||||
- required-opps
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -17,12 +17,14 @@ description: |
|
||||
include/dt-bindings/clock/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/clock/qcom,sm8550-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8450-gpucc.h
|
||||
include/dt-bindings/reset/qcom,sm8650-gpucc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8450-gpucc
|
||||
- qcom,sm8550-gpucc
|
||||
- qcom,sm8650-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@ -13,12 +13,16 @@ description: |
|
||||
Qualcomm TCSR clock control module provides the clocks, resets and
|
||||
power domains on SM8550
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8550-tcsr
|
||||
- enum:
|
||||
- qcom,sm8550-tcsr
|
||||
- qcom,sm8650-tcsr
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
|
||||
106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
Normal file
106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
Normal file
@ -0,0 +1,106 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller for SM8650
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8650.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8650-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Display's AHB clock
|
||||
- description: sleep clock
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY0
|
||||
- description: VCO DIV clock from DP PHY0
|
||||
- description: Link clock from DP PHY1
|
||||
- description: VCO DIV clock from DP PHY1
|
||||
- description: Link clock from DP PHY2
|
||||
- description: VCO DIV clock from DP PHY2
|
||||
- description: Link clock from DP PHY3
|
||||
- description: VCO DIV clock from DP PHY3
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm8650-dispcc";
|
||||
reg = <0x0af00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&gcc GCC_DISP_AHB_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp0_phy 0>,
|
||||
<&dp0_phy 1>,
|
||||
<&dp1_phy 0>,
|
||||
<&dp1_phy 1>,
|
||||
<&dp2_phy 0>,
|
||||
<&dp2_phy 1>,
|
||||
<&dp3_phy 0>,
|
||||
<&dp3_phy 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
...
|
||||
65
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
Normal file
65
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8650
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8650
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8650-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board Always On XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 1 Pipe clock source
|
||||
- description: PCIE 1 Phy Auxiliary clock source
|
||||
- description: UFS Phy Rx symbol 0 clock source
|
||||
- description: UFS Phy Rx symbol 1 clock source
|
||||
- description: UFS Phy Tx symbol 0 clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm8650-gcc";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie0_phy>,
|
||||
<&pcie1_phy>,
|
||||
<&pcie_1_phy_aux_clk>,
|
||||
<&ufs_mem_phy 0>,
|
||||
<&ufs_mem_phy 1>,
|
||||
<&ufs_mem_phy 2>,
|
||||
<&usb_1_qmpphy>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on X1E80100
|
||||
|
||||
maintainers:
|
||||
- Rajendra Nayak <quic_rjendra@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on X1E80100
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,x1e80100-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIe 3 pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: PCIe 5 pipe clock
|
||||
- description: PCIe 6a pipe clock
|
||||
- description: PCIe 6b pipe clock
|
||||
- description: USB QMP Phy 0 clock source
|
||||
- description: USB QMP Phy 1 clock source
|
||||
- description: USB QMP Phy 2 clock source
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the CX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,x1e80100-gcc";
|
||||
reg = <0x00100000 0x200000>;
|
||||
clocks = <&bi_tcxo_div2>,
|
||||
<&sleep_clk>,
|
||||
<&pcie3_phy>,
|
||||
<&pcie4_phy>,
|
||||
<&pcie5_phy>,
|
||||
<&pcie6a_phy>,
|
||||
<&pcie6b_phy>,
|
||||
<&usb_1_ss0_qmpphy 0>,
|
||||
<&usb_1_ss1_qmpphy 1>,
|
||||
<&usb_1_ss2_qmpphy 2>;
|
||||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -24,6 +24,7 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-aal
|
||||
- mediatek,mt8183-disp-aal
|
||||
- mediatek,mt8195-mdp3-aal
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2712-disp-aal
|
||||
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- mediatek,mt2701-disp-color
|
||||
- mediatek,mt8167-disp-color
|
||||
- mediatek,mt8173-disp-color
|
||||
- mediatek,mt8195-mdp3-color
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-color
|
||||
|
||||
@ -34,6 +34,10 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt6795-dsi
|
||||
- const: mediatek,mt8173-dsi
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-dsi
|
||||
- const: mediatek,mt8183-dsi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -23,7 +23,11 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8195-disp-ethdr
|
||||
oneOf:
|
||||
- const: mediatek,mt8195-disp-ethdr
|
||||
- items:
|
||||
- const: mediatek,mt8188-disp-ethdr
|
||||
- const: mediatek,mt8195-disp-ethdr
|
||||
|
||||
reg:
|
||||
maxItems: 7
|
||||
|
||||
@ -1,88 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MDP RDMA
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description:
|
||||
The MediaTek MDP RDMA stands for Read Direct Memory Access.
|
||||
It provides real time data to the back-end panel driver, such as DSI,
|
||||
DPI and DP_INTF.
|
||||
It contains one line buffer to store the sufficient pixel data.
|
||||
RDMA device node must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8195-vdo1-rdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: RDMA Clock
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
- mediatek,gce-client-reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/power/mt8195-power.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
#include <dt-bindings/memory/mt8195-memory-port.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rdma@1c104000 {
|
||||
compatible = "mediatek,mt8195-vdo1-rdma";
|
||||
reg = <0 0x1c104000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
|
||||
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
|
||||
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
|
||||
};
|
||||
};
|
||||
@ -24,9 +24,13 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-merge
|
||||
- mediatek,mt8195-disp-merge
|
||||
- mediatek,mt8195-mdp3-merge
|
||||
- items:
|
||||
- const: mediatek,mt6795-disp-merge
|
||||
- const: mediatek,mt8173-disp-merge
|
||||
- items:
|
||||
- const: mediatek,mt8188-disp-merge
|
||||
- const: mediatek,mt8195-disp-merge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -26,6 +26,7 @@ properties:
|
||||
- mediatek,mt8173-disp-ovl
|
||||
- mediatek,mt8183-disp-ovl
|
||||
- mediatek,mt8192-disp-ovl
|
||||
- mediatek,mt8195-mdp3-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-ovl
|
||||
|
||||
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Display Padding
|
||||
|
||||
maintainers:
|
||||
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description:
|
||||
Padding provides ability to add pixels to width and height of a layer with
|
||||
specified colors. Due to hardware design, Mixer in VDOSYS1 requires
|
||||
width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
|
||||
we need Padding to deal with odd width.
|
||||
Please notice that even if the Padding is in bypass mode, settings in
|
||||
register must be cleared to 0, or undefined behaviors could happen.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8188-disp-padding
|
||||
- mediatek,mt8195-mdp3-padding
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Padding's clocks
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
GCE (Global Command Engine) is a multi-core micro processor that helps
|
||||
its clients to execute commands without interrupting CPU. This property
|
||||
describes GCE client's information that is composed by 4 fields.
|
||||
1. Phandle of the GCE (there may be several GCE processors)
|
||||
2. Sub-system ID defined in the dt-binding like a user ID
|
||||
(Please refer to include/dt-bindings/gce/<chip>-gce.h)
|
||||
3. Offset from base address of the subsys you are at
|
||||
4. Size of the register the client needs
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: Phandle of the GCE
|
||||
- description: Subsys ID defined in the dt-binding
|
||||
- description: Offset from base address of the subsys
|
||||
- description: Size of register
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- clocks
|
||||
- mediatek,gce-client-reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
|
||||
#include <dt-bindings/power/mediatek,mt8188-power.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
padding0: padding@1c11d000 {
|
||||
compatible = "mediatek,mt8188-disp-padding";
|
||||
reg = <0 0x1c11d000 0 0x1000>;
|
||||
clocks = <&vdosys1 CLK_VDO1_PADDING0>;
|
||||
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
|
||||
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
|
||||
};
|
||||
};
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt8173-disp-split
|
||||
- mediatek,mt8195-mdp3-split
|
||||
- items:
|
||||
- const: mediatek,mt6795-disp-split
|
||||
- const: mediatek,mt8173-disp-split
|
||||
@ -38,6 +39,21 @@ properties:
|
||||
the power controller specified by phandle. See
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml for details.
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: SPLIT Clock
|
||||
@ -48,6 +64,17 @@ required:
|
||||
- power-domains
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8195-mdp3-split
|
||||
|
||||
then:
|
||||
required:
|
||||
- mediatek,gce-client-reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -40,6 +40,11 @@ properties:
|
||||
- rockchip,rk3288-mali
|
||||
- samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-mali
|
||||
- const: samsung,exynos5433-mali
|
||||
- const: arm,mali-t760
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3399-mali
|
||||
|
||||
@ -11,9 +11,21 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-chipid
|
||||
- samsung,exynos850-chipid
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos4210-chipid
|
||||
- samsung,exynos850-chipid
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-chipid
|
||||
- samsung,exynos7-chipid
|
||||
- const: samsung,exynos4210-chipid
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-chipid
|
||||
- samsung,exynosautov9-chipid
|
||||
- samsung,exynosautov920-chipid
|
||||
- const: samsung,exynos850-chipid
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -25,7 +25,16 @@ properties:
|
||||
- samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
|
||||
- samsung,exynos5260-hsi2c # Exynos5260
|
||||
- samsung,exynos7-hsi2c # Exynos7
|
||||
- samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850
|
||||
- samsung,exynosautov9-hsi2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-hsi2c
|
||||
- tesla,fsd-hsi2c
|
||||
- const: samsung,exynos7-hsi2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos850-hsi2c
|
||||
- const: samsung,exynosautov9-hsi2c
|
||||
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
|
||||
deprecated: true
|
||||
|
||||
|
||||
@ -11,14 +11,20 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2410-i2c
|
||||
- samsung,s3c2440-i2c
|
||||
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
|
||||
- samsung,s3c2440-hdmiphy-i2c
|
||||
# For s3c2440-like I2C used as a host to SATA PHY controller on an
|
||||
# internal bus:
|
||||
- samsung,exynos5-sata-phy-i2c
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,s3c2410-i2c
|
||||
- samsung,s3c2440-i2c
|
||||
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
|
||||
- samsung,s3c2440-hdmiphy-i2c
|
||||
# For s3c2440-like I2C used as a host to SATA PHY controller on an
|
||||
# internal bus:
|
||||
- samsung,exynos5-sata-phy-i2c
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-i2c
|
||||
- samsung,exynos850-i2c
|
||||
- const: samsung,s3c2440-i2c
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
@ -11,18 +11,23 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos-adc-v1 # Exynos5250
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
|
||||
- samsung,exynos7-adc
|
||||
- samsung,s3c2410-adc
|
||||
- samsung,s3c2416-adc
|
||||
- samsung,s3c2440-adc
|
||||
- samsung,s3c2443-adc
|
||||
- samsung,s3c6410-adc
|
||||
- samsung,s5pv210-adc
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,exynos-adc-v1 # Exynos5250
|
||||
- samsung,exynos-adc-v2
|
||||
- samsung,exynos3250-adc
|
||||
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
|
||||
- samsung,exynos7-adc
|
||||
- samsung,s3c2410-adc
|
||||
- samsung,s3c2416-adc
|
||||
- samsung,s3c2440-adc
|
||||
- samsung,s3c2443-adc
|
||||
- samsung,s3c6410-adc
|
||||
- samsung,s5pv210-adc
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-adc
|
||||
- const: samsung,exynos7-adc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
152
Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml
Normal file
152
Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml
Normal file
@ -0,0 +1,152 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM6115 Network-On-Chip interconnect
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
The Qualcomm SM6115 interconnect providers support adjusting the
|
||||
bandwidth requirements between the various NoC fabrics.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-bimc
|
||||
- qcom,sm6115-cnoc
|
||||
- qcom,sm6115-snoc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
# Child node's properties
|
||||
patternProperties:
|
||||
'^interconnect-[a-z0-9]+$':
|
||||
type: object
|
||||
description:
|
||||
The interconnect providers do not have a separate QoS register space,
|
||||
but share parent's space.
|
||||
|
||||
$ref: qcom,rpm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-clk-virt
|
||||
- qcom,sm6115-mmrt-virt
|
||||
- qcom,sm6115-mmnrt-virt
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,rpm-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6115-cnoc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: USB-NoC AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: usb_axi
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6115-snoc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: CPU-NoC AXI clock.
|
||||
- description: UFS-NoC AXI clock.
|
||||
- description: USB-NoC AXI clock.
|
||||
- description: IPA clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cpu_axi
|
||||
- const: ufs_axi
|
||||
- const: usb_axi
|
||||
- const: ipa
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6115-bimc
|
||||
- qcom,sm6115-clk-virt
|
||||
- qcom,sm6115-mmrt-virt
|
||||
- qcom,sm6115-mmnrt-virt
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks: false
|
||||
clock-names: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
snoc: interconnect@1880000 {
|
||||
compatible = "qcom,sm6115-snoc";
|
||||
reg = <0x01880000 0x60200>;
|
||||
clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
|
||||
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&rpmcc RPM_SMD_IPA_CLK>;
|
||||
clock-names = "cpu_axi",
|
||||
"ufs_axi",
|
||||
"usb_axi",
|
||||
"ipa";
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
qup_virt: interconnect-clk {
|
||||
compatible = "qcom,sm6115-clk-virt";
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
mmnrt_virt: interconnect-mmnrt {
|
||||
compatible = "qcom,sm6115-mmnrt-virt";
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
mmrt_virt: interconnect-mmrt {
|
||||
compatible = "qcom,sm6115-mmrt-virt";
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cnoc: interconnect@1900000 {
|
||||
compatible = "qcom,sm6115-cnoc";
|
||||
reg = <0x01900000 0x8200>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
@ -0,0 +1,136 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
|
||||
|
||||
maintainers:
|
||||
- Abel Vesa <abel.vesa@linaro.org>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
RPMh interconnect providers support system bandwidth requirements through
|
||||
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
|
||||
able to communicate with the BCM through the Resource State Coordinator (RSC)
|
||||
associated with each execution environment. Provider nodes must point to at
|
||||
least one RPMh device child node pertaining to their RSC and each provider
|
||||
can map to multiple RPMh resources.
|
||||
|
||||
See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8650-aggre1-noc
|
||||
- qcom,sm8650-aggre2-noc
|
||||
- qcom,sm8650-clk-virt
|
||||
- qcom,sm8650-cnoc-main
|
||||
- qcom,sm8650-config-noc
|
||||
- qcom,sm8650-gem-noc
|
||||
- qcom,sm8650-lpass-ag-noc
|
||||
- qcom,sm8650-lpass-lpiaon-noc
|
||||
- qcom,sm8650-lpass-lpicx-noc
|
||||
- qcom,sm8650-mc-virt
|
||||
- qcom,sm8650-mmss-noc
|
||||
- qcom,sm8650-nsp-noc
|
||||
- qcom,sm8650-pcie-anoc
|
||||
- qcom,sm8650-system-noc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,rpmh-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8650-clk-virt
|
||||
- qcom,sm8650-mc-virt
|
||||
then:
|
||||
properties:
|
||||
reg: false
|
||||
else:
|
||||
required:
|
||||
- reg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8650-pcie-anoc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: aggre-NOC PCIe AXI clock
|
||||
- description: cfg-NOC PCIe a-NOC AHB clock
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8650-aggre1-noc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: aggre UFS PHY AXI clock
|
||||
- description: aggre USB3 PRIM AXI clock
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8650-aggre2-noc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: RPMH CC IPA clock
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8650-aggre1-noc
|
||||
- qcom,sm8650-aggre2-noc
|
||||
- qcom,sm8650-pcie-anoc
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
else:
|
||||
properties:
|
||||
clocks: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk_virt: interconnect-0 {
|
||||
compatible = "qcom,sm8650-clk-virt";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,sm8650-aggre1-noc";
|
||||
reg = <0x016e0000 0x14400>;
|
||||
#interconnect-cells = <2>;
|
||||
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
|
||||
|
||||
maintainers:
|
||||
- Rajendra Nayak <quic_rjendra@quicinc.com>
|
||||
- Abel Vesa <abel.vesa@linaro.org>
|
||||
|
||||
description: |
|
||||
RPMh interconnect providers support system bandwidth requirements through
|
||||
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
|
||||
able to communicate with the BCM through the Resource State Coordinator (RSC)
|
||||
associated with each execution environment. Provider nodes must point to at
|
||||
least one RPMh device child node pertaining to their RSC and each provider
|
||||
can map to multiple RPMh resources.
|
||||
|
||||
See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,x1e80100-aggre1-noc
|
||||
- qcom,x1e80100-aggre2-noc
|
||||
- qcom,x1e80100-clk-virt
|
||||
- qcom,x1e80100-cnoc-cfg
|
||||
- qcom,x1e80100-cnoc-main
|
||||
- qcom,x1e80100-gem-noc
|
||||
- qcom,x1e80100-lpass-ag-noc
|
||||
- qcom,x1e80100-lpass-lpiaon-noc
|
||||
- qcom,x1e80100-lpass-lpicx-noc
|
||||
- qcom,x1e80100-mc-virt
|
||||
- qcom,x1e80100-mmss-noc
|
||||
- qcom,x1e80100-nsp-noc
|
||||
- qcom,x1e80100-pcie-center-anoc
|
||||
- qcom,x1e80100-pcie-north-anoc
|
||||
- qcom,x1e80100-pcie-south-anoc
|
||||
- qcom,x1e80100-system-noc
|
||||
- qcom,x1e80100-usb-center-anoc
|
||||
- qcom,x1e80100-usb-north-anoc
|
||||
- qcom,x1e80100-usb-south-anoc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,rpmh-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,x1e80100-clk-virt
|
||||
- qcom,x1e80100-mc-virt
|
||||
then:
|
||||
properties:
|
||||
reg: false
|
||||
else:
|
||||
required:
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk_virt: interconnect-0 {
|
||||
compatible = "qcom,x1e80100-clk-virt";
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
aggre1_noc: interconnect@16e0000 {
|
||||
compatible = "qcom,x1e80100-aggre1-noc";
|
||||
reg = <0x016e0000 0x14400>;
|
||||
#interconnect-cells = <2>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
@ -66,6 +66,7 @@ properties:
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-plic
|
||||
- sophgo,cv1800b-plic
|
||||
- sophgo,cv1812h-plic
|
||||
- sophgo,sg2042-plic
|
||||
- thead,th1520-plic
|
||||
- const: thead,c900-plic
|
||||
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Media Data Path 3 Film Grain
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description:
|
||||
Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add
|
||||
the film grain according to the AOMedia Video 1 (AV1) standard.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8195-mdp3-fg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
display@14002000 {
|
||||
compatible = "mediatek,mt8195-mdp3-fg";
|
||||
reg = <0x14002000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Media Data Path 3 HDR
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description:
|
||||
A Media Data Path 3 (MDP3) component used to perform conversion from
|
||||
High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8195-mdp3-hdr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
display@14004000 {
|
||||
compatible = "mediatek,mt8195-mdp3-hdr";
|
||||
reg = <0x14004000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
|
||||
};
|
||||
@ -20,8 +20,14 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: mediatek,mt8183-mdp3-rdma
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-rdma
|
||||
- mediatek,mt8195-mdp3-rdma
|
||||
- mediatek,mt8195-vdo1-rdma
|
||||
- items:
|
||||
- const: mediatek,mt8188-vdo1-rdma
|
||||
- const: mediatek,mt8195-vdo1-rdma
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -45,6 +51,14 @@ properties:
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
mediatek,scp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the System Control Processor (SCP) used for initializing
|
||||
and stopping the MDP3, for sending frame data locations to the MDP3's
|
||||
VPU and to install Inter-Processor Interrupt handlers to control
|
||||
processing states.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
@ -52,6 +66,7 @@ properties:
|
||||
items:
|
||||
- description: RDMA clock
|
||||
- description: RSZ clock
|
||||
minItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
@ -60,16 +75,72 @@ properties:
|
||||
items:
|
||||
- description: used for 1st data pipe from RDMA
|
||||
- description: used for 2nd data pipe from RDMA
|
||||
- description: used for 3rd data pipe from RDMA
|
||||
- description: used for 4th data pipe from RDMA
|
||||
- description: used for the data pipe from SPLIT
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- mediatek,gce-events
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
- mboxes
|
||||
- '#dma-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-mdp3-rdma
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
mboxes:
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- mboxes
|
||||
- mediatek,gce-events
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8195-mdp3-rdma
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
mboxes:
|
||||
minItems: 5
|
||||
|
||||
required:
|
||||
- mediatek,gce-events
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8195-vdo1-rdma
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -80,16 +151,17 @@ examples:
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/memory/mt8183-larb-port.h>
|
||||
|
||||
mdp3_rdma0: mdp3-rdma0@14001000 {
|
||||
compatible = "mediatek,mt8183-mdp3-rdma";
|
||||
reg = <0x14001000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
|
||||
<CMDQ_EVENT_MDP_RDMA0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
|
||||
<&mmsys CLK_MM_MDP_RSZ1>;
|
||||
iommus = <&iommu>;
|
||||
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
|
||||
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
|
||||
dma-controller@14001000 {
|
||||
compatible = "mediatek,mt8183-mdp3-rdma";
|
||||
reg = <0x14001000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
|
||||
<CMDQ_EVENT_MDP_RDMA0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
|
||||
<&mmsys CLK_MM_MDP_RSZ1>;
|
||||
iommus = <&iommu>;
|
||||
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
|
||||
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
@ -15,9 +15,13 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-rsz
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-mdp3-rsz
|
||||
- const: mediatek,mt8183-mdp3-rsz
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Media Data Path 3 STITCH
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description:
|
||||
One of Media Data Path 3 (MDP3) components used to combine multiple video frame
|
||||
with overlapping fields of view to produce a segmented panorame.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8195-mdp3-stitch
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
display@14003000 {
|
||||
compatible = "mediatek,mt8195-mdp3-stitch";
|
||||
reg = <0x14003000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_STITCH>;
|
||||
};
|
||||
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Media Data Path 3 Tone Curve Conversion
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
description:
|
||||
Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components.
|
||||
It is used to handle the tone mapping of various gamma curves in order to
|
||||
achieve HDR10 effects. This helps adapt the content to the color and
|
||||
brightness range that standard display devices typically support.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8195-mdp3-tcc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
display@1400b000 {
|
||||
compatible = "mediatek,mt8195-mdp3-tcc";
|
||||
reg = <0x1400b000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Media Data Path 3 Two-Dimensional Sharpness
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- Moudy Ho <moudy.ho@mediatek.com>
|
||||
|
||||
description:
|
||||
Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component
|
||||
used to perform image edge sharpening and enhance vividness and contrast.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8195-mdp3-tdshp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,gce-client-reg:
|
||||
description:
|
||||
The register of display function block to be set by gce. There are 4 arguments,
|
||||
such as gce node, subsys id, offset and register size. The subsys id that is
|
||||
mapping to the register of display function blocks is defined in the gce header
|
||||
include/dt-bindings/gce/<chip>-gce.h of each chips.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
items:
|
||||
- description: phandle of GCE
|
||||
- description: GCE subsys id
|
||||
- description: register offset
|
||||
- description: register size
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- mediatek,gce-client-reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/gce/mt8195-gce.h>
|
||||
|
||||
display@14007000 {
|
||||
compatible = "mediatek,mt8195-mdp3-tdshp";
|
||||
reg = <0x14007000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
|
||||
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
|
||||
};
|
||||
@ -15,9 +15,13 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- enum:
|
||||
- mediatek,mt8183-mdp3-wrot
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8195-mdp3-wrot
|
||||
- const: mediatek,mt8183-mdp3-wrot
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -50,6 +54,9 @@ properties:
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -58,6 +65,7 @@ required:
|
||||
- power-domains
|
||||
- clocks
|
||||
- iommus
|
||||
- '#dma-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -68,13 +76,14 @@ examples:
|
||||
#include <dt-bindings/power/mt8183-power.h>
|
||||
#include <dt-bindings/memory/mt8183-larb-port.h>
|
||||
|
||||
mdp3_wrot0: mdp3-wrot0@14005000 {
|
||||
compatible = "mediatek,mt8183-mdp3-wrot";
|
||||
reg = <0x14005000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
|
||||
<CMDQ_EVENT_MDP_WROT0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
||||
iommus = <&iommu>;
|
||||
dma-controller@14005000 {
|
||||
compatible = "mediatek,mt8183-mdp3-wrot";
|
||||
reg = <0x14005000 0x1000>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
|
||||
<CMDQ_EVENT_MDP_WROT0_EOF>;
|
||||
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
|
||||
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
||||
iommus = <&iommu>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
@ -85,7 +85,7 @@ examples:
|
||||
};
|
||||
|
||||
i2s@11440000 {
|
||||
compatible = "samsung,exynos7-i2s";
|
||||
compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
|
||||
reg = <0x11440000 0x100>;
|
||||
dmas = <&adma 0>, <&adma 2>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
@ -14,15 +14,22 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos4210-dw-mshc
|
||||
- samsung,exynos4412-dw-mshc
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc-smu
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- axis,artpec8-dw-mshc
|
||||
oneOf:
|
||||
- enum:
|
||||
- axis,artpec8-dw-mshc
|
||||
- samsung,exynos4210-dw-mshc
|
||||
- samsung,exynos4412-dw-mshc
|
||||
- samsung,exynos5250-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc
|
||||
- samsung,exynos5420-dw-mshc-smu
|
||||
- samsung,exynos7-dw-mshc
|
||||
- samsung,exynos7-dw-mshc-smu
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-dw-mshc-smu
|
||||
- samsung,exynos7885-dw-mshc-smu
|
||||
- samsung,exynos850-dw-mshc-smu
|
||||
- const: samsung,exynos7-dw-mshc-smu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -29,7 +29,11 @@ properties:
|
||||
- samsung,exynos4210-pwm # 32-bit, Exynos
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-pwm
|
||||
- samsung,exynos7-pwm
|
||||
- samsung,exynosautov9-pwm
|
||||
- samsung,exynosautov920-pwm
|
||||
- tesla,fsd-pwm
|
||||
- const: samsung,exynos4210-pwm
|
||||
|
||||
reg:
|
||||
|
||||
@ -22,6 +22,10 @@ properties:
|
||||
- enum:
|
||||
- milkv,duo
|
||||
- const: sophgo,cv1800b
|
||||
- items:
|
||||
- enum:
|
||||
- sophgo,huashan-pi
|
||||
- const: sophgo,cv1812h
|
||||
- items:
|
||||
- enum:
|
||||
- milkv,pioneer
|
||||
|
||||
@ -17,6 +17,11 @@ properties:
|
||||
- samsung,s3c2416-rtc
|
||||
- samsung,s3c2443-rtc
|
||||
- samsung,s3c6410-rtc
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-rtc
|
||||
- samsung,exynos850-rtc
|
||||
- const: samsung,s3c6410-rtc
|
||||
- const: samsung,exynos3250-rtc
|
||||
deprecated: true
|
||||
|
||||
|
||||
@ -18,9 +18,6 @@ description: |+
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: samsung,exynosautov9-uart
|
||||
- const: samsung,exynos850-uart
|
||||
- enum:
|
||||
- apple,s5l-uart
|
||||
- axis,artpec8-uart
|
||||
@ -29,6 +26,20 @@ properties:
|
||||
- samsung,exynos4210-uart
|
||||
- samsung,exynos5433-uart
|
||||
- samsung,exynos850-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7-uart
|
||||
- tesla,fsd-uart
|
||||
- const: samsung,exynos4210-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-uart
|
||||
- const: samsung,exynos5433-uart
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynosautov9-uart
|
||||
- samsung,exynosautov920-uart
|
||||
- const: samsung,exynos850-uart
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -158,3 +158,36 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
system-controller@ff63c000 {
|
||||
compatible = "amlogic,meson-axg-hhi-sysctrl", "simple-mfd", "syscon";
|
||||
reg = <0xff63c000 0x400>;
|
||||
|
||||
clock-controller {
|
||||
compatible = "amlogic,axg-clkc";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
};
|
||||
|
||||
power-controller {
|
||||
compatible = "amlogic,meson-axg-pwrc";
|
||||
#power-domain-cells = <1>;
|
||||
amlogic,ao-sysctrl = <&sysctrl_AO>;
|
||||
|
||||
resets = <&reset_viu>,
|
||||
<&reset_venc>,
|
||||
<&reset_vcbus>,
|
||||
<&reset_vencl>,
|
||||
<&reset_vid_lock>;
|
||||
reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
|
||||
clocks = <&clk_vpu>, <&clk_vapb>;
|
||||
clock-names = "vpu", "vapb";
|
||||
};
|
||||
|
||||
phy {
|
||||
compatible = "amlogic,axg-mipi-pcie-analog-phy";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -41,7 +41,6 @@ properties:
|
||||
- mediatek,mt8173-pwrap
|
||||
- mediatek,mt8183-pwrap
|
||||
- mediatek,mt8186-pwrap
|
||||
- mediatek,mt8188-pwrap
|
||||
- mediatek,mt8195-pwrap
|
||||
- mediatek,mt8365-pwrap
|
||||
- mediatek,mt8516-pwrap
|
||||
@ -50,6 +49,11 @@ properties:
|
||||
- mediatek,mt8186-pwrap
|
||||
- mediatek,mt8195-pwrap
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-pwrap
|
||||
- const: mediatek,mt8195-pwrap
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
||||
@ -22,8 +22,10 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8183-svs
|
||||
- mediatek,mt8186-svs
|
||||
- mediatek,mt8188-svs
|
||||
- mediatek,mt8192-svs
|
||||
- mediatek,mt8195-svs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -28,6 +28,8 @@ properties:
|
||||
- rockchip,rk3588-sys-grf
|
||||
- rockchip,rk3588-pcie3-phy-grf
|
||||
- rockchip,rk3588-pcie3-pipe-grf
|
||||
- rockchip,rk3588-vo-grf
|
||||
- rockchip,rk3588-vop-grf
|
||||
- rockchip,rv1108-usbgrf
|
||||
- const: syscon
|
||||
- items:
|
||||
|
||||
@ -15,6 +15,7 @@ select:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-pmu
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4212-pmu
|
||||
@ -35,6 +36,7 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- google,gs101-pmu
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4212-pmu
|
||||
@ -48,6 +50,14 @@ properties:
|
||||
- samsung,exynos850-pmu
|
||||
- samsung-s5pv210-pmu
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos7885-pmu
|
||||
- samsung,exynosautov9-pmu
|
||||
- samsung,exynosautov920-pmu
|
||||
- tesla,fsd-pmu
|
||||
- const: samsung,exynos7-pmu
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos3250-pmu
|
||||
|
||||
@ -24,7 +24,9 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: samsung,exynosautov9-usi
|
||||
- enum:
|
||||
- samsung,exynosautov9-usi
|
||||
- samsung,exynosautov920-usi
|
||||
- const: samsung,exynos850-usi
|
||||
- enum:
|
||||
- samsung,exynos850-usi
|
||||
@ -155,7 +157,7 @@ examples:
|
||||
};
|
||||
|
||||
hsi2c_0: i2c@13820000 {
|
||||
compatible = "samsung,exynosautov9-hsi2c";
|
||||
compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
|
||||
reg = <0x13820000 0xc0>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -14,9 +14,14 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- google,gs101-apm-sysreg
|
||||
- google,gs101-peric0-sysreg
|
||||
- google,gs101-peric1-sysreg
|
||||
- samsung,exynos3-sysreg
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
- samsung,exynosautov920-peric0-sysreg
|
||||
- samsung,exynosautov920-peric1-sysreg
|
||||
- tesla,fsd-cam-sysreg
|
||||
- tesla,fsd-fsys0-sysreg
|
||||
- tesla,fsd-fsys1-sysreg
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
|
||||
$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx Zynq Platforms
|
||||
@ -132,6 +132,11 @@ properties:
|
||||
- const: xlnx,zynqmp-smk-k26
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: AMD MicroBlaze V (QEMU)
|
||||
items:
|
||||
- const: qemu,mbv
|
||||
- const: amd,mbv
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -0,0 +1,116 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Audio Front End (AFE) PCM controller for mt2701
|
||||
|
||||
description:
|
||||
The AFE PCM node must be a subnode of the MediaTek audsys device tree node.
|
||||
|
||||
maintainers:
|
||||
- Eugen Hristev <eugen.hristev@collabora.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt2701-audio
|
||||
- mediatek,mt7622-audio
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: AFE interrupt
|
||||
- description: ASYS interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: afe
|
||||
- const: asys
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: audio infra sys clock
|
||||
- description: top audio mux 1
|
||||
- description: top audio mux 2
|
||||
- description: top audio sys a1 clock
|
||||
- description: top audio sys a2 clock
|
||||
- description: i2s0 source selection
|
||||
- description: i2s1 source selection
|
||||
- description: i2s2 source selection
|
||||
- description: i2s3 source selection
|
||||
- description: i2s0 source divider
|
||||
- description: i2s1 source divider
|
||||
- description: i2s2 source divider
|
||||
- description: i2s3 source divider
|
||||
- description: i2s0 master clock
|
||||
- description: i2s1 master clock
|
||||
- description: i2s2 master clock
|
||||
- description: i2s3 master clock
|
||||
- description: i2so0 hopping clock
|
||||
- description: i2so1 hopping clock
|
||||
- description: i2so2 hopping clock
|
||||
- description: i2so3 hopping clock
|
||||
- description: i2si0 hopping clock
|
||||
- description: i2si1 hopping clock
|
||||
- description: i2si2 hopping clock
|
||||
- description: i2si3 hopping clock
|
||||
- description: asrc0 output clock
|
||||
- description: asrc1 output clock
|
||||
- description: asrc2 output clock
|
||||
- description: asrc3 output clock
|
||||
- description: audio front end pd clock
|
||||
- description: audio front end conn pd clock
|
||||
- description: top audio a1 sys pd
|
||||
- description: top audio a2 sys pd
|
||||
- description: audio merge interface pd
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: infra_sys_audio_clk
|
||||
- const: top_audio_mux1_sel
|
||||
- const: top_audio_mux2_sel
|
||||
- const: top_audio_a1sys_hp
|
||||
- const: top_audio_a2sys_hp
|
||||
- const: i2s0_src_sel
|
||||
- const: i2s1_src_sel
|
||||
- const: i2s2_src_sel
|
||||
- const: i2s3_src_sel
|
||||
- const: i2s0_src_div
|
||||
- const: i2s1_src_div
|
||||
- const: i2s2_src_div
|
||||
- const: i2s3_src_div
|
||||
- const: i2s0_mclk_en
|
||||
- const: i2s1_mclk_en
|
||||
- const: i2s2_mclk_en
|
||||
- const: i2s3_mclk_en
|
||||
- const: i2so0_hop_ck
|
||||
- const: i2so1_hop_ck
|
||||
- const: i2so2_hop_ck
|
||||
- const: i2so3_hop_ck
|
||||
- const: i2si0_hop_ck
|
||||
- const: i2si1_hop_ck
|
||||
- const: i2si2_hop_ck
|
||||
- const: i2si3_hop_ck
|
||||
- const: asrc0_out_ck
|
||||
- const: asrc1_out_ck
|
||||
- const: asrc2_out_ck
|
||||
- const: asrc3_out_ck
|
||||
- const: audio_afe_pd
|
||||
- const: audio_afe_conn_pd
|
||||
- const: audio_a1sys_pd
|
||||
- const: audio_a2sys_pd
|
||||
- const: audio_mrgif_pd
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
@ -1,146 +0,0 @@
|
||||
Mediatek AFE PCM controller for mt2701
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following.
|
||||
- "mediatek,mt2701-audio"
|
||||
- "mediatek,mt7622-audio"
|
||||
- interrupts: should contain AFE and ASYS interrupts
|
||||
- interrupt-names: should be "afe" and "asys"
|
||||
- power-domains: should define the power domain
|
||||
- clocks: Must contain an entry for each entry in clock-names
|
||||
See ../clocks/clock-bindings.txt for details
|
||||
- clock-names: should have these clock names:
|
||||
"infra_sys_audio_clk",
|
||||
"top_audio_mux1_sel",
|
||||
"top_audio_mux2_sel",
|
||||
"top_audio_a1sys_hp",
|
||||
"top_audio_a2sys_hp",
|
||||
"i2s0_src_sel",
|
||||
"i2s1_src_sel",
|
||||
"i2s2_src_sel",
|
||||
"i2s3_src_sel",
|
||||
"i2s0_src_div",
|
||||
"i2s1_src_div",
|
||||
"i2s2_src_div",
|
||||
"i2s3_src_div",
|
||||
"i2s0_mclk_en",
|
||||
"i2s1_mclk_en",
|
||||
"i2s2_mclk_en",
|
||||
"i2s3_mclk_en",
|
||||
"i2so0_hop_ck",
|
||||
"i2so1_hop_ck",
|
||||
"i2so2_hop_ck",
|
||||
"i2so3_hop_ck",
|
||||
"i2si0_hop_ck",
|
||||
"i2si1_hop_ck",
|
||||
"i2si2_hop_ck",
|
||||
"i2si3_hop_ck",
|
||||
"asrc0_out_ck",
|
||||
"asrc1_out_ck",
|
||||
"asrc2_out_ck",
|
||||
"asrc3_out_ck",
|
||||
"audio_afe_pd",
|
||||
"audio_afe_conn_pd",
|
||||
"audio_a1sys_pd",
|
||||
"audio_a2sys_pd",
|
||||
"audio_mrgif_pd";
|
||||
- assigned-clocks: list of input clocks and dividers for the audio system.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- assigned-clocks-parents: parent of input clocks of assigned clocks.
|
||||
- assigned-clock-rates: list of clock frequencies of assigned clocks.
|
||||
|
||||
Must be a subnode of MediaTek audsys device tree node.
|
||||
See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
|
||||
|
||||
Example:
|
||||
|
||||
audsys: audio-subsystem@11220000 {
|
||||
compatible = "mediatek,mt2701-audsys", "syscon";
|
||||
...
|
||||
|
||||
afe: audio-controller {
|
||||
compatible = "mediatek,mt2701-audio";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "afe", "asys";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
||||
|
||||
clocks = <&infracfg CLK_INFRA_AUDIO>,
|
||||
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_48K_TIMING>,
|
||||
<&topckgen CLK_TOP_AUD_44K_TIMING>,
|
||||
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
|
||||
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
|
||||
<&audsys CLK_AUD_I2SO1>,
|
||||
<&audsys CLK_AUD_I2SO2>,
|
||||
<&audsys CLK_AUD_I2SO3>,
|
||||
<&audsys CLK_AUD_I2SO4>,
|
||||
<&audsys CLK_AUD_I2SIN1>,
|
||||
<&audsys CLK_AUD_I2SIN2>,
|
||||
<&audsys CLK_AUD_I2SIN3>,
|
||||
<&audsys CLK_AUD_I2SIN4>,
|
||||
<&audsys CLK_AUD_ASRCO1>,
|
||||
<&audsys CLK_AUD_ASRCO2>,
|
||||
<&audsys CLK_AUD_ASRCO3>,
|
||||
<&audsys CLK_AUD_ASRCO4>,
|
||||
<&audsys CLK_AUD_AFE>,
|
||||
<&audsys CLK_AUD_AFE_CONN>,
|
||||
<&audsys CLK_AUD_A1SYS>,
|
||||
<&audsys CLK_AUD_A2SYS>,
|
||||
<&audsys CLK_AUD_AFE_MRGIF>;
|
||||
|
||||
clock-names = "infra_sys_audio_clk",
|
||||
"top_audio_mux1_sel",
|
||||
"top_audio_mux2_sel",
|
||||
"top_audio_a1sys_hp",
|
||||
"top_audio_a2sys_hp",
|
||||
"i2s0_src_sel",
|
||||
"i2s1_src_sel",
|
||||
"i2s2_src_sel",
|
||||
"i2s3_src_sel",
|
||||
"i2s0_src_div",
|
||||
"i2s1_src_div",
|
||||
"i2s2_src_div",
|
||||
"i2s3_src_div",
|
||||
"i2s0_mclk_en",
|
||||
"i2s1_mclk_en",
|
||||
"i2s2_mclk_en",
|
||||
"i2s3_mclk_en",
|
||||
"i2so0_hop_ck",
|
||||
"i2so1_hop_ck",
|
||||
"i2so2_hop_ck",
|
||||
"i2so3_hop_ck",
|
||||
"i2si0_hop_ck",
|
||||
"i2si1_hop_ck",
|
||||
"i2si2_hop_ck",
|
||||
"i2si3_hop_ck",
|
||||
"asrc0_out_ck",
|
||||
"asrc1_out_ck",
|
||||
"asrc2_out_ck",
|
||||
"asrc3_out_ck",
|
||||
"audio_afe_pd",
|
||||
"audio_afe_conn_pd",
|
||||
"audio_a1sys_pd",
|
||||
"audio_a2sys_pd",
|
||||
"audio_mrgif_pd";
|
||||
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
|
||||
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
|
||||
<&topckgen CLK_TOP_AUD2PLL_90M>;
|
||||
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
|
||||
};
|
||||
};
|
||||
@ -44,13 +44,18 @@ properties:
|
||||
frequencies supported by Exynos7 I2S and 7.1 channel TDM support
|
||||
for playback and capture TDM (Time division multiplexing) to allow
|
||||
transfer of multiple channel audio data on single data line.
|
||||
enum:
|
||||
- samsung,s3c6410-i2s
|
||||
- samsung,s5pv210-i2s
|
||||
- samsung,exynos5420-i2s
|
||||
- samsung,exynos7-i2s
|
||||
- samsung,exynos7-i2s1
|
||||
- tesla,fsd-i2s
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,s3c6410-i2s
|
||||
- samsung,s5pv210-i2s
|
||||
- samsung,exynos5420-i2s
|
||||
- samsung,exynos7-i2s
|
||||
- samsung,exynos7-i2s1
|
||||
- tesla,fsd-i2s
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos5433-i2s
|
||||
- const: samsung,exynos7-i2s
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
@ -38,6 +38,7 @@ properties:
|
||||
- enum:
|
||||
- allwinner,sun20i-d1-clint
|
||||
- sophgo,cv1800b-clint
|
||||
- sophgo,cv1812h-clint
|
||||
- thead,th1520-clint
|
||||
- const: thead,c900-clint
|
||||
- items:
|
||||
|
||||
@ -294,6 +294,8 @@ patternProperties:
|
||||
description: CompuLab Ltd.
|
||||
"^congatec,.*":
|
||||
description: congatec GmbH
|
||||
"^coolpi,.*":
|
||||
description: cool-pi.com
|
||||
"^coreriver,.*":
|
||||
description: CORERIVER Semiconductor Co.,Ltd.
|
||||
"^corpro,.*":
|
||||
@ -352,6 +354,8 @@ patternProperties:
|
||||
description: Digi International Inc.
|
||||
"^digilent,.*":
|
||||
description: Diglent, Inc.
|
||||
"^dimonoff,.*":
|
||||
description: Dimonoff inc.
|
||||
"^diodes,.*":
|
||||
description: Diodes, Inc.
|
||||
"^dioo,.*":
|
||||
@ -597,6 +601,8 @@ patternProperties:
|
||||
description: Hewlett Packard Enterprise
|
||||
"^hsg,.*":
|
||||
description: HannStar Display Co.
|
||||
"^htc,.*":
|
||||
description: HTC Corporation
|
||||
"^huawei,.*":
|
||||
description: Huawei Technologies Co., Ltd.
|
||||
"^hugsun,.*":
|
||||
@ -1179,6 +1185,8 @@ patternProperties:
|
||||
description: Shenzhen Roofull Technology Co, Ltd
|
||||
"^roseapplepi,.*":
|
||||
description: RoseapplePi.org
|
||||
"^rve,.*":
|
||||
description: Recharge Véhicule Électrique (RVE) inc.
|
||||
"^saef,.*":
|
||||
description: Saef Technology Limited
|
||||
"^samsung,.*":
|
||||
@ -1434,6 +1442,8 @@ patternProperties:
|
||||
description: TPO
|
||||
"^tq,.*":
|
||||
description: TQ-Systems GmbH
|
||||
"^transpeed,.*":
|
||||
description: Transpeed
|
||||
"^traverse,.*":
|
||||
description: Traverse Technologies Australia Pty Ltd
|
||||
"^tronfy,.*":
|
||||
|
||||
@ -16,14 +16,19 @@ description: |+
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c2410-wdt # for S3C2410
|
||||
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
|
||||
- samsung,exynos5250-wdt # for Exynos5250
|
||||
- samsung,exynos5420-wdt # for Exynos5420
|
||||
- samsung,exynos7-wdt # for Exynos7
|
||||
- samsung,exynos850-wdt # for Exynos850
|
||||
- samsung,exynosautov9-wdt # for Exynosautov9
|
||||
oneOf:
|
||||
- enum:
|
||||
- samsung,s3c2410-wdt # for S3C2410
|
||||
- samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
|
||||
- samsung,exynos5250-wdt # for Exynos5250
|
||||
- samsung,exynos5420-wdt # for Exynos5420
|
||||
- samsung,exynos7-wdt # for Exynos7
|
||||
- samsung,exynos850-wdt # for Exynos850
|
||||
- samsung,exynosautov9-wdt # for Exynosautov9
|
||||
- items:
|
||||
- enum:
|
||||
- tesla,fsd-wdt
|
||||
- const: samsung,exynos7-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
14
MAINTAINERS
14
MAINTAINERS
@ -2321,8 +2321,7 @@ F: arch/arm/boot/dts/marvell/armada*
|
||||
F: arch/arm/boot/dts/marvell/kirkwood*
|
||||
F: arch/arm/configs/mvebu_*_defconfig
|
||||
F: arch/arm/mach-mvebu/
|
||||
F: arch/arm64/boot/dts/marvell/armada*
|
||||
F: arch/arm64/boot/dts/marvell/cn913*
|
||||
F: arch/arm64/boot/dts/marvell/
|
||||
F: drivers/clk/mvebu/
|
||||
F: drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
F: drivers/cpufreq/armada-8k-cpufreq.c
|
||||
@ -3008,6 +3007,7 @@ F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
|
||||
F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
|
||||
F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
|
||||
F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
|
||||
F: Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
|
||||
F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
|
||||
F: arch/arm/mach-zynq/
|
||||
F: drivers/clocksource/timer-cadence-ttc.c
|
||||
@ -9001,6 +9001,16 @@ S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
|
||||
F: drivers/firmware/google/
|
||||
|
||||
GOOGLE TENSOR SoC SUPPORT
|
||||
M: Peter Griffin <peter.griffin@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
|
||||
F: arch/arm64/boot/dts/exynos/google/
|
||||
F: drivers/clk/samsung/clk-gs101.c
|
||||
F: include/dt-bindings/clock/google,gs101.h
|
||||
|
||||
GPD POCKET FAN DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
|
||||
@ -232,6 +232,12 @@
|
||||
interrupt-names = "nand";
|
||||
};
|
||||
|
||||
serial@4400 {
|
||||
compatible = "brcm,bcm63138-hs-uart", "brcm,bcmbca-hs-uart";
|
||||
reg = <0x4400 0x1e0>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bootlut: bootlut@8000 {
|
||||
compatible = "brcm,bcm63138-bootlut";
|
||||
reg = <0x8000 0x50>;
|
||||
|
||||
@ -165,6 +165,24 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* PHY 0..4 are internal to the MV88E6060 switch but appear
|
||||
* as independent devices.
|
||||
*/
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
/* Altima AMI101L used by the WAN port */
|
||||
phy9: ethernet-phy@9 {
|
||||
reg = <9>;
|
||||
};
|
||||
@ -181,21 +199,25 @@
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
|
||||
@ -768,7 +768,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand0: nand@ff900000 {
|
||||
nand0: nand-controller@ff900000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
compatible = "altr,socfpga-denali-nand";
|
||||
|
||||
@ -669,7 +669,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@ffb90000 {
|
||||
nand: nand-controller@ffb90000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "altr,socfpga-denali-nand";
|
||||
|
||||
@ -17,8 +17,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <3>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -124,8 +124,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -129,8 +129,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -174,8 +174,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -121,8 +121,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
|
||||
m25p,fast-read;
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -229,8 +229,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
@ -246,8 +244,6 @@
|
||||
spi-max-frequency = <100000000>;
|
||||
m25p,fast-read;
|
||||
|
||||
cdns,page-size = <256>;
|
||||
cdns,block-size = <16>;
|
||||
cdns,read-delay = <4>;
|
||||
cdns,tshsl-ns = <50>;
|
||||
cdns,tsd2d-ns = <50>;
|
||||
|
||||
@ -95,7 +95,7 @@
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = <0 0 3000 1>;
|
||||
gpio-fan,speed-map = <0 0>, <3000 1>;
|
||||
pinctrl-0 = <&fan_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
@ -149,39 +149,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
switch: switch@10 {
|
||||
switch: ethernet-switch@10 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
ethernet = <ð1>;
|
||||
phy-mode = "rgmii-id";
|
||||
@ -196,25 +194,25 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switchphy0: switchphy@0 {
|
||||
switchphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy1: switchphy@1 {
|
||||
switchphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy2: switchphy@2 {
|
||||
switchphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
switchphy3: switchphy@3 {
|
||||
switchphy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
interrupt-parent = <&switch>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@ -25,9 +25,9 @@
|
||||
|
||||
gpio-fan {
|
||||
gpio-fan,speed-map =
|
||||
< 0 3
|
||||
950 2
|
||||
1400 1
|
||||
1800 0>;
|
||||
< 0 3>,
|
||||
< 950 2>,
|
||||
<1400 1>,
|
||||
<1800 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -106,10 +106,10 @@
|
||||
|
||||
gpio-fan {
|
||||
gpio-fan,speed-map =
|
||||
< 0 3
|
||||
800 2
|
||||
1050 1
|
||||
1300 0>;
|
||||
< 0 3>,
|
||||
< 800 2>,
|
||||
<1050 1>,
|
||||
<1300 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -113,14 +113,14 @@
|
||||
&gpio2 0 GPIO_ACTIVE_HIGH
|
||||
&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
1000 1
|
||||
1150 2
|
||||
1350 4
|
||||
1500 3
|
||||
1650 5
|
||||
1750 6
|
||||
1900 7 >;
|
||||
gpio-fan,speed-map = < 0 0>,
|
||||
<1000 1>,
|
||||
<1150 2>,
|
||||
<1350 4>,
|
||||
<1500 3>,
|
||||
<1650 5>,
|
||||
<1750 6>,
|
||||
<1900 7>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
||||
@ -77,51 +77,49 @@
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
#address-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&switch_interrupt_pins>;
|
||||
pinctrl-names = "default";
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
@ -142,11 +140,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii";
|
||||
reg = <0>;
|
||||
@ -158,55 +156,55 @@
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
reg = <8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan9";
|
||||
phy-handle = <&phy1>;
|
||||
@ -214,7 +212,7 @@
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
port@a {
|
||||
ethernet-port@a {
|
||||
/* 88X3310P external phy */
|
||||
label = "lan10";
|
||||
phy-handle = <&phy2>;
|
||||
|
||||
@ -7,66 +7,66 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
|
||||
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <8>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@10 {
|
||||
ethernet-port@10 {
|
||||
reg = <10>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
@ -83,35 +83,35 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@1 {
|
||||
switch0phy0: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@2 {
|
||||
switch0phy1: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@3 {
|
||||
switch0phy2: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@4 {
|
||||
switch0phy3: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@5 {
|
||||
switch0phy4: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@6 {
|
||||
switch0phy5: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@7 {
|
||||
switch0phy6: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@8 {
|
||||
switch0phy7: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -11,42 +11,42 @@
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
|
||||
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "2500base-x";
|
||||
ethernet = <ð1>;
|
||||
@ -63,19 +63,19 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@14 {
|
||||
switch0phy3: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -158,42 +158,40 @@
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
switch@0 {
|
||||
ethernet-switch@0 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
phy-mode = "sgmii";
|
||||
ethernet = <ð2>;
|
||||
|
||||
@ -131,14 +131,14 @@
|
||||
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio1 17 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio1 16 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
1500 1
|
||||
2500 2
|
||||
3000 3
|
||||
3400 4
|
||||
3700 5
|
||||
3900 6
|
||||
4000 7>;
|
||||
gpio-fan,speed-map = < 0 0>,
|
||||
<1500 1>,
|
||||
<2500 2>,
|
||||
<3000 3>,
|
||||
<3400 4>,
|
||||
<3700 5>,
|
||||
<3900 6>,
|
||||
<4000 7>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user