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ASoC: fsl_sai: add sai master mode support
When sai works on master mode, set its bit clock and frame clock. SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk will select proper MCLK source, then calculate and set the bit clock divider. After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add hw_free() to disable the mclk. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Zidan Wang
Mark Brown
parent
b787f68c36
commit
c3ecef21c3
@ -1,7 +1,7 @@
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/*
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* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
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*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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* Copyright 2012-2015 Freescale Semiconductor, Inc.
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*
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* This program is free software, you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -251,12 +251,14 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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sai->is_slave_mode = true;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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sai->is_slave_mode = true;
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break;
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default:
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return -EINVAL;
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@ -288,6 +290,79 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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return ret;
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}
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static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
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unsigned long clk_rate;
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u32 savediv = 0, ratio, savesub = freq;
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u32 id;
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int ret = 0;
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/* Don't apply to slave mode */
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if (sai->is_slave_mode)
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return 0;
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for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
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clk_rate = clk_get_rate(sai->mclk_clk[id]);
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if (!clk_rate)
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continue;
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ratio = clk_rate / freq;
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ret = clk_rate - ratio * freq;
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/*
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* Drop the source that can not be
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* divided into the required rate.
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*/
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if (ret != 0 && clk_rate / ret < 1000)
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continue;
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dev_dbg(dai->dev,
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"ratio %d for freq %dHz based on clock %ldHz\n",
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ratio, freq, clk_rate);
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if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
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ratio /= 2;
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else
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continue;
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if (ret < savesub) {
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savediv = ratio;
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sai->mclk_id[tx] = id;
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savesub = ret;
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}
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if (ret == 0)
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break;
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}
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if (savediv == 0) {
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dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
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tx ? 'T' : 'R', freq);
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return -EINVAL;
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}
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if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
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FSL_SAI_CR2_MSEL_MASK,
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FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
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FSL_SAI_CR2_DIV_MASK, savediv - 1);
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} else {
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regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
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FSL_SAI_CR2_MSEL_MASK,
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FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
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FSL_SAI_CR2_DIV_MASK, savediv - 1);
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}
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dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
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sai->mclk_id[tx], savediv, savesub);
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return 0;
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}
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static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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@ -297,6 +372,24 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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unsigned int channels = params_channels(params);
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u32 word_width = snd_pcm_format_width(params_format(params));
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u32 val_cr4 = 0, val_cr5 = 0;
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int ret;
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if (!sai->is_slave_mode) {
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ret = fsl_sai_set_bclk(cpu_dai, tx,
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2 * word_width * params_rate(params));
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if (ret)
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return ret;
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/* Do not enable the clock if it is already enabled */
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if (!(sai->mclk_streams & BIT(substream->stream))) {
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ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
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if (ret)
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return ret;
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sai->mclk_streams |= BIT(substream->stream);
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}
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}
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if (!sai->is_dsp_mode)
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val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
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@ -322,6 +415,22 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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return 0;
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}
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static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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if (!sai->is_slave_mode &&
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sai->mclk_streams & BIT(substream->stream)) {
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clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
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sai->mclk_streams &= ~BIT(substream->stream);
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}
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return 0;
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}
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static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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@ -428,6 +537,7 @@ static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
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.set_sysclk = fsl_sai_set_dai_sysclk,
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.set_fmt = fsl_sai_set_dai_fmt,
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.hw_params = fsl_sai_hw_params,
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.hw_free = fsl_sai_hw_free,
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.trigger = fsl_sai_trigger,
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.startup = fsl_sai_startup,
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.shutdown = fsl_sai_shutdown,
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@ -600,8 +710,9 @@ static int fsl_sai_probe(struct platform_device *pdev)
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sai->bus_clk = NULL;
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}
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for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
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sprintf(tmp, "mclk%d", i + 1);
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sai->mclk_clk[0] = sai->bus_clk;
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for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
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sprintf(tmp, "mclk%d", i);
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sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
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if (IS_ERR(sai->mclk_clk[i])) {
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dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
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@ -72,13 +72,15 @@
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/* SAI Transmit and Recieve Configuration 2 Register */
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#define FSL_SAI_CR2_SYNC BIT(30)
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#define FSL_SAI_CR2_MSEL_MASK (0xff << 26)
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#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
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#define FSL_SAI_CR2_MSEL_BUS 0
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#define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
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#define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
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#define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
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#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
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#define FSL_SAI_CR2_BCP BIT(25)
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#define FSL_SAI_CR2_BCD_MSTR BIT(24)
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#define FSL_SAI_CR2_DIV_MASK 0xff
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/* SAI Transmit and Recieve Configuration 3 Register */
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#define FSL_SAI_CR3_TRCE BIT(16)
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@ -120,7 +122,7 @@
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#define FSL_SAI_CLK_MAST2 2
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#define FSL_SAI_CLK_MAST3 3
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#define FSL_SAI_MCLK_MAX 3
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#define FSL_SAI_MCLK_MAX 4
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/* SAI data transfer numbers per DMA request */
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#define FSL_SAI_MAXBURST_TX 6
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@ -132,11 +134,14 @@ struct fsl_sai {
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struct clk *bus_clk;
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struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
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bool is_slave_mode;
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bool is_lsb_first;
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bool is_dsp_mode;
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bool sai_on_imx;
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bool synchronous[2];
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unsigned int mclk_id[2];
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unsigned int mclk_streams;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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