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iio: dac: ad5766: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: fd9373e41b ("iio: dac: ad5766: add driver support for AD5766")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-54-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:33 +01:00
parent b378722a3e
commit c32be7f035
1 changed files with 1 additions and 1 deletions
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drivers/iio/dac/ad5766.c
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@ -123,7 +123,7 @@ struct ad5766_state {
u32 d32;
u16 w16[2];
u8 b8[4];
} data[3] ____cacheline_aligned;
} data[3] __aligned(IIO_DMA_MINALIGN);
};
struct ad5766_span_tbl {